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991.
Duncan Temple Lang 《Journal of computational and graphical statistics》2013,22(3):423-451
Abstract Statistical environments such as S, R, XLisp-Stat, and others have had a dramatic effect on the way we, statistics practitioners, think about data and statistical methodology. However, the possibilities and challenges introduced by recent technological developments and the general ways we use computing conflict with the computational model of these systems. This article explores some of these challenges and identifies the need to support easy integration of functionality from other domains, and to export statistical methodology to other audiences and applications, both statically and dynamically. Existing systems can be improved in these domains with some already implemented extensions (see Section 5). However, the development of a new environment and computational model that exploits modern tools designed to handle many general aspects of these challenges appears more promising as a long-term approach. We present the architecture for such a new model named Omegahat. It lends itself to entirely new statistical computing paradigms. It is highly extensible at both the user and programmer level, and also encourages the development of new environments for different user groups. The Omegahat interactive language offers a continuity between the different programming tasks and levels via optional type checking and seamless access between the interpreted user language and the implementation language, Java. Parallel and distributed computing, network and database access, interactive graphics, and many other aspects of statistical computing are directly accessible to the user as a consequence of this seamless access. We describe the benefits of using Java as the implementation language for the environment and several innovative features of the user-level language which promise to assist development of software that can be used in many contexts. We also outline how this architecture can be integrated with existing environments such as R and S. The ideas are drawn from work within the Omega Project for Statistical Computing. The project provides open-source software for researching and developing next generation statistical computing tools. 相似文献
992.
We study the conditional sojourn time distributions of processor sharing (PS), foreground background processor sharing (FBPS)
and shortest remaining processing time first (SRPT) scheduling disciplines on an event where the job size of a customer arriving
in stationarity is smaller than exactly k≥0 out of the preceding m≥k arrivals. Then, conditioning on the preceding event, the sojourn time distribution of this newly arriving customer behaves
asymptotically the same as if the customer were served in isolation with a server of rate (1−ρ)/(k+1) for PS/FBPS, and (1−ρ) for SRPT, respectively, where ρ is the traffic intensity. Hence, the introduced notion of conditional limits allows us to distinguish the asymptotic performance
of the studied schedulers by showing that SRPT exhibits considerably better asymptotic behavior for relatively smaller jobs
than PS/FBPS.
Inspired by the preceding results, we propose an approximation to the SRPT discipline based on a novel adaptive job grouping
mechanism that uses relative size comparison of a newly arriving job to the preceding m arrivals. Specifically, if the newly arriving job is smaller than k and larger than m−k of the previous m jobs, it is routed into class k. Then, the classes of smaller jobs are served with higher priorities using the static priority scheduling. The good performance
of this mechanism, even for a small number of classes m+1, is demonstrated using the asymptotic queueing analysis under the heavy-tailed job requirements. We also discuss refinements
of the comparison grouping mechanism that improve the accuracy of job classification at the expense of a small additional
complexity.
This work is supported by NSF Grant 0615126. 相似文献
993.
提出了一种基于数字信号处理器(DSP)的语音无线混沌数字通信系统设计与硬件实现的新方案.根据Runge-Kutta算法和变量比例扩张变换,以多涡卷广义Jerk系统为例,对其连续混沌系统作离散化处理,产生作为语音数据加密与解密的混沌数字序列.在芯片型号TMS320VC5509APGE的DSP技术平台上,利用无线发送器和无线接收器nRF2401,实现了语音无线混沌数字通信.给出了技术设计与硬件实现结果,证实了该方案的可行性. 相似文献
994.
Ali Khajeh-Saeed Stephen Poole J. Blair Perot 《Journal of computational physics》2010,229(11):4247-4258
Finding regions of similarity between two very long data streams is a computationally intensive problem referred to as sequence alignment. Alignment algorithms must allow for imperfect sequence matching with different starting locations and some gaps and errors between the two data sequences. Perhaps the most well known application of sequence matching is the testing of DNA or protein sequences against genome databases. The Smith–Waterman algorithm is a method for precisely characterizing how well two sequences can be aligned and for determining the optimal alignment of those two sequences. Like many applications in computational science, the Smith–Waterman algorithm is constrained by the memory access speed and can be accelerated significantly by using graphics processors (GPUs) as the compute engine. In this work we show that effective use of the GPU requires a novel reformulation of the Smith–Waterman algorithm. The performance of this new version of the algorithm is demonstrated using the SSCA#1 (Bioinformatics) benchmark running on one GPU and on up to four GPUs executing in parallel. The results indicate that for large problems a single GPU is up to 45 times faster than a CPU for this application, and the parallel implementation shows linear speed up on up to 4 GPUs. 相似文献
995.
介绍了一种新型铁电存储器FM25CL64,分析了TMS320VC5402 DSP的SPI引导装载模式,给出了一种基于铁电存储器FM25CL64的DSP脱机独立运行系统的设计方案,该方案已成功地应用到一种语音门锁系统中。 相似文献
996.
997.
Mladen Berekovic Mladen Berekovic Tim Niggemeier 《Journal of Signal Processing Systems》2008,50(2):201-229
A scalable, distributed, processor architecture is presented that emphasizes on high performance computing for digital signal
processing applications by combining high frequency design techniques with a very high degree of parallel processing on a
chip. The architecture is based on a superscalar processor model with a modified Tomasulo scheme that was extended to eliminate
all central control structures for the data flow and to support simultaneous instruction issue from multiple independent threads
[simultaneously multi-threaded (SMT)]. Consequent application of fine clustering reduces the cycle-time for wire-sensitive
building blocks of the processor like the register file and the scheduling window and leads to a distributed architecture
model, where independent thread processing units, arithmetic logic units, registers files and memories are distributed across
the chip and communicate with each other by special network. A special communication protocol replaces broadcasting and associative
compare of destination tags in a centralised instruction scheduler with explicit operand transfer instructions, thus decentralizing
the control of the data flow to the greatest extent. As a result, the processor cycle time does neither depend on the issue
bandwidth of a single thread nor on the execution bandwidth of the SMT processor. This makes the performance of the architecture
scalable with both the number of function and the number of thread units without having any impact on the processors cycle-time.
Performance and scalability of the proposed microarchitecture is demonstrated with critical signal processing kernels from
the MPEG-4 video coding standard on a cycle-true simulator.
相似文献
Tim NiggemeierEmail: |
998.
Tay-Jyi Lin Shin-Kai Chen Yu-Ting Kuo Chih-Wei Liu Pi-Chen Hsiao 《Journal of Signal Processing Systems》2008,51(3):209-223
This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications.
The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time
of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance
(estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is
also adopted to reduce the program sizes to 24.1∼26.0%. The DSP has been fabricated in the UMC 0.13 μm 1P8M Copper Logic Process,
and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2 × 3.15 mm2 including 160 KB on-chip SRAM.
相似文献
Chih-Wei LiuEmail: |
999.
J2EE技术在构架数字城市网站发布系统中的应用与实践 总被引:1,自引:0,他引:1
论述J2EE技术在构架数字城市网站发布系统中的应用思路,通过J2EE多层体系结构对系统划分层次,可以克服传统的网站发布系统的缺点。在充分利用数据库技术和网络技术的基础上,采用第二代Web发布机制,提供真正的动态内容管理方式,从而既简化系统的设计步骤,也为程序员提供灵活的设计构架,同时提高系统的运行效率。最后借助于一个在此构架之下已经开发完成的数字城市网站,展示了这种构架技术所具有的通用性、可伸缩性和可移植性等特点。 相似文献
1000.
分析市场主要网络设备模拟器的特点,开发出基于浏览器/服务器(Browser/Server)架构的、面向网络实践教学或培训的网络设备模拟器软件系统,并就开发中的关键技术进行了详细的阐述。模拟器前端使用Flash的ActionScript提取设备命令信息,后台采用Java语言开发仿真引擎,通过XML进行前、后端信息的传递。模拟器具有多用户、快速响应、通用设备等特点。 相似文献