Interface modulated electron mobility enhancement in core-shell nanowires

The transport properties of core-shell nanowires (CSNWs) under interface modulation and confinement are investigated based on the atomic-bond-relaxation (ABR) correlation mechanism and Fermi's golden rule. An analytical expression for the relationship between carrier mobility and interface mismatch strain is derived and the influence of size, shell thickness and alloyed layer on effective mass, band structures, and deformation potential constant are studied. It is found that interface modulation can not only reduce the lattice mismatch to optimize the band alignment, but also participate in the carrier transport for enhancing mobility. Moreover, the underlying mechanism regarding the interface shape dependence of transport properties in CSNWs is clarified. The great enhancement of electron mobility suggests that the interface modulation may become a potential pathway to improving the performance of nanoelectronic devices.     

High-speed CMOS demultiplexer with redundant multi-valued logic

This paper describes an 11-Gb/s CMOS demultiplexer with redundant multi-valued logic. The proposed circuit receives serial binary data which is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the redundant multi-valued logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. The circuit is designed with a 0.35?µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The demultiplexer is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43?mW. This circuit is expected to operate at a higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.     

The forward bias current density–voltage–temperature (J–V–T) characteristics of Al–SiO2–pSi (MIS) Schottky diodes

Metal–insulator–semiconductor Schottky diodes were fabricated to investigate the tunnel effect and the dominant carrier transport mechanism by using current density–voltage (J–V) and capacitance–voltage (C–V) measurements in the temperature range of 295–370?K. The slope of the ln?J–V curves was almost constant value over the nearly four decades of current and the forward bias current density J is found to be proportional to J_o (T) exp(AV). The values of N_ss estimated from J–V and C–V measurements decreased with increasing temperature. The temperature dependence of the barrier heights obtained from forward bias J–V was found to be entirely different than that from the reverse bias C–V characteristics. All these behaviours confirmed that the prepared samples have a tunnel effect and the current transport mechanism in the temperature range of 295–370?K was predominated by a trap-assisted multi-step tunnelling, although the Si wafer has low doping concentration and the measurements were made at moderate temperature.     

Pulse amplitude-modulated time-based interface for off-chip interconnect

An increased number of bits pulse amplitude-modulated differential-time signalling interface for off-chip interconnect is introduced in this article by combining the differential time signalling (DTS) technique with the pulse amplitude-modulation (PAM) approach. Applying the PAM to the DTS-transmitted signal increases the total number of the transmitted bits per symbol while maintaining the transmitted signal bandwidth. 4-bit 6 Gb/s DTS serial link has been designed and simulated using 65 nm CMOS mixed signal technology. 5-bit 7.5 Gb/s and 6-bit 9 Gb/s amplitude-modulated DTS serial links have been designed, simulated and compared to the 6 Gb/s DTS serial link. The three serial links use 1.5 Gb/s as input clock signal. In the amplitude-modulated DTS-transmitted signal, the rising and falling edges of the input clock signal are modulated in time as well as the transmitted signal amplitude is modulated. A reference clock pulse is generated from the input clock signal and embedded on the transmitted signal to be used as reference timing at the receiver circuit. The design details of the designed links are presented in the article. The 9 Gb/s link uses a 60 cm 4003C Rogers substrate as a transmission channel. The transmitted signal spectrum is presented and compared for the three designed links. The total power consumption of the 9 Gb/s amplitude-modulated DTS interface is less than 25 mW.     

计算机与路由器同步开关装置的设计与制作

为了节约电能,延长路由器使用寿命,设计一种办公室用计算机与路由器同步开关的装置,只要有一台计算机开机,就能自动打开路由器工作电源,最后一台计算机关机,又能自动关闭路由器电源。此设计利用计算机双绞线中四根备用线中的其中两根,引出计算机USB接口的5V电源控制继电器吸合,从而控制路由器开关,实现路由器与计算机工作同步。     

Spike in transient photocurrent of organic solar cell: Exciton dissociation at interface

The effect of exciton interfacial dissociation on transient photocurrent (TPC) in a single-layer organic solar cell is investigated within a time-dependent device model. The spike observed in TPC experiments is attributed to exciton dissociation at the electrode/organic interface. In comparison with the observed negative signal of transient photovoltage (TPV), the spike more directly reflects the charge processes at the interface. Moreover, numerical results show that the spike of TPC is sensitive to the voltage applied on the device and the hole mobility of the organic semiconductor. Further investigation on the spike by the favorable TPC technique is suggested to provide details about the exciton and carrier processes at the interface.     

金属栅/高k基FinFET研究进展

对比传统的平面型晶体管,总结了三维立体结构FinFET器件的结构特性。结合MOS器件栅介质材料研究进展,分别从纯硅基、多晶硅/高k基以及金属栅/高k基三个阶段综述了Fin-FET器件的发展历程,分析了各阶段FinFET器件的材料特性及其在等比缩小时所面临的关键问题,并着重从延迟时间、可靠性和功耗三方面分析了金属栅/高k基FinFET应用于22 nm器件的性能优势。基于短沟道效应以及界面态对器件性能的影响,探讨了FinFET器件尺寸等比缩小可能产生的负面效应及其解决办法。分析了FinFET器件下一步可能的发展方向,主要为高迁移率沟道材料、立体型栅结构以及基于新原理的电子器件。     

增强现实研究进展与核心技术(上)

介绍了增强现实概念及其研究进展,阐述了增强现实的显示技术、交互技术、注册技术等核心技术,最后分析了用户界面等限制增强现实技术发展的要素。     

基于c-Si(P)衬底的a-Si/c-Si异质结模拟研究

本文中研究了影响 a-Si/c-Si 异质结界面复合的主要因素： 表面固定电荷 ,缺陷态载流子俘获界面： ,以及界面缺陷态密度 。当缺陷能级 接近c-Si本征能级,且 满足时,缺陷态复合中心复合速度达到最大。AFORS-HET 软件模拟显示, a-Si/c-Si界面能带不连续显著影响电池Voc、界面缺陷态密度大于1*1010 cm-2.eV-1时,界面态密度的增加会严重降低电池Voc,但其对电池电流密度影响不大。对于c-Si (P)/a-Si (P ) 结构异质结,C-Si衬底的势垒 和a-Si材料内的势垒 对降低c-Si (P)/a-Si (P ) 结构的接触电阻和界面复合速度,表现各不相同。     

模拟路灯控制系统设计

模拟路灯控制系统以SCT89C58为控制核心。以DS1302为时钟源,以红外线传感器、光学传感器对移动物体和环境明暗变化进行信息采集,通过软件编程能实时显示时钟和设定、显示开关灯时间,控制整条支路根据设定时间、环境明暗、交通情况自动开灯、关灯、调节亮灯状态或独立控制单灯开和关,并能根据布设在支路单元上的光敏器件的采集信息进行路灯故障声光报警。在设计中编程语言使用了C51,并采用模块化设计方法 ,不仅易于编程和调试,也可减小软件故障率和提高软件的可靠性。因此,本系统具有性能优良、稳定可靠、节能环保的优点。