一种提高微电路外壳使用可靠性的方法

简要分析了白瓷双列直插外壳的失效模式和失效机理，并进行了模拟实验，通过对实验结果的分析，提出对成品微电路进行二次电镀能够提高其外壳的使用可靠性。     

混合集成电路激光功能调值技术

本文提出了激光功能微调技术在高精度混合集成电路上的应用，讨论了关键技术问题，并以实例具体说明。该技术的应用为研制高精度混合集成电路开辟了新途径。     

STN—LCD的新进展

STN-LCD采用新的取向层,消除了残象;采用新的驱动波形,消除了串扰;采用二(口恶)烷、卤化物、链烯基、醚和二苯乙炔,改进了液晶料材的性能,使STN-LCD获得高的对比度、快的响应速度、低的驱动电压;采用有源矩阵驱动方法,消除了帧响应,使STN-LCD获得高的对比度、高的亮度及视频响应速度;使用温度跟踪电路,自动跟踪STN-LCD的阀值电压,使STN-LCD获得宽的工作温度。     

Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.     

用于多种组装技术的厚膜导体复合结构

厚膜导体Ｐｄ－Ａｇ／Ａｕ、Ｐｔ－Ｐｄ－Ａｕ／Ａｕ平面复合结构，Ｐｄ－Ａｇ／Ａｕ立体复合结构可使多种组装技术相互兼容。立体复合结构还可有效地降低导体线电阻，减少线损耗。而且，其超声键合性尤佳     

电路板故障诊断中神经网络信息融合技术的应用

将信息融合技术应用到导弹电子设备的电路板故障诊断之中．提出了一种基于红外热成像实验的温度故障隶属度函数构造形式以及改进的BP神经网络算法。进行了BP神经网络信息融合故障诊断的实验研究．从结果看信息融合能较好地解决电路板元件故障诊断的不确定性问题。     

Deposition conditions in tailoring the morphology of highly porous reticular films prepared by electrostatic spray deposition (ESD) technique

Spongy-like reticular structure is a unique morphology fabricated by electrostatic spray deposition (ESD) technique. The effects of solvent, substrate temperature, precursor feeding rate, static electric field strength, and deposition time on tailoring the reticular structure were investigated. Scanning electron microscopy was used to observe the film morphology. MnO_x or LiMn₂O₄ were selected as the model materials. It is found that in addition to the conventional solvent butyl carbitol, other kinds of solvents such as ethylene glycol and propylene glycol can also be used to obtain reticular films at a suitable substrate temperature. Porous films with a low cross-linking degree pore structure can be prepared by increasing precursor feeding rate or decreasing substrate temperature. Increasing the deposition time or the electric field strength helps to obtain reticular films with more homogeneous pore size distribution. In addition, the addition of a high boiling-point solvent in mixed alcohol solvent results in the increase of proper substrate temperature. It is concluded that the fluidity of the spray droplets on the surface of a hot substrate is an important factor to form a reticular film.     

Mössbauer effect study of the decagonal quasicrystal Al65Co15Cu20

The ⁵⁷Fe Mössbauer effect study at 5.0 K and in an external magnetic field of 9.0 T on a high-quality stable decagonal quasicrystal Al₆₅Co₁₅Cu_19.9Fe_0.1 is presented. It is shown that the iron atoms are located in two distinct classes of sites. The values of the principal component of the electric field gradient tensor and the asymmetry parameter at these sites are, respectively, ?1.90(10)?×?10²¹ V/m², 0.97(15) and ?3.95(12)?×?10²¹ V/m², 0.00(17).     

Memory management optimization problems for integrated circuit simulators

In hardware design, it is necessary to simulate the anticipated behavior of the integrated circuit before it is actually cast in silicon. As simulation procedures are long due to the great number of tests to be performed, optimization of the simulation code is of prime importance. This paper describes two mathematical models for the minimization of the memory access times for a cycle-based simulator.An integrated circuit being viewed as a directed acyclic graph, the problem consists in building a graph order on the vertices, compatible with the relation order induced by the graph, in order to minimize a cost function that represents the memory access time. For both proposed cost functions, we show that the corresponding problems are NP-complete. However, we show that the special cases where the graphs are in-trees or out-trees can be solved in polynomial time.     

交流源作用下介观RLC电路系统量子态随时间的演化

根据量子不变量理论，同时考虑介观电容器极板间电子波函数的耦合作用和电路的耗散,研究介观RLC电路系统在交流电流源作用下动力学的演化过程，并且得到描述系统量子态随时间的演化算符.进一步的分析结果表明，介观RLC电路系统的波函数将由任意的初态演化到一般的压缩态. 关键词： 介观RLC电路 交变电源 不变量理论 时间演化算符