一种带接口的CMOS10位电流型乘法D／A转换器

介绍了一种带接口的单片ＣＭＯＳ１０位电流型乘法Ｄ／Ａ转换器的设计及工作方式。着重阐述逻辑电平转换、控制逻辑的结构设计及其工作方式。在不修调电阻网络的情况下，该Ｄ／Ａ转换器在５Ｖ、１５Ｖ下，其线性误差、微分误差、满刻度误差均能达到１０位精度     

GaAs、InP集成电路技术的发展——1992年IEEE GaAs IC讨论会评述

本文介绍了1992年IEEE GaAs IC讨论会的概况,并依据这次国际会议所发表的论文,以GaAs、InP集成电路的技术路线为主线,介绍和评述了GaAs基PHEMT,HBT,MESFET以及InP基HEMT、HBT等集成电路的现状与发展。     

Defect formation in epitaxial oxide dielectric layers due to substrate surface relief

Defects were characterized in epitaxial (001) CeO₂ films deposited and planarizedin situ on patterned (001) LaAlO₃ substrates by ion beam assisted deposition (IBAD). A hill and valley structure with steps running parallel to the [100] LaAlO₃ axis was produced on the surface of the substrate by photolithography and ion beam etching prior to film deposition. A conformai epitaxial CeO₂ layer of ∼ 100 nm thickness was deposited on the heated substrate by e-beam evaporation. Lattice-matching between the e-beam film and the substrate was of the type: (001) CeO₂∥(001) LaAlO₃ and [110] CeO₂∥[100] LaAlO₃. Evaporative deposition of additional film onto the conformai layer was accompanied by bombardment with a 500 eV argon/oxygen ion beam to promotein situ planarization. Extreme lattice misfit for the orientation (001) CeO₂∥(001)LaAlO₃ and [001] CeO₂∥[001] LaAlO₃ caused formation of dislocations in the e-beam CeO₂ film in the vicinity of individual ledges in the substrate surface. Coherence of the CeO₂ film was locally lost in the step regions of the hill and valley structure. The large patterned steps, which are composed of numerous adjacent ledges in the LaAlO₃ surface, caused nucleation of CeO₂ with a tilt misalignment of up to ∼5‡ about the substrate [100]. Nucleation and growth of nonepitaxial CeO₂ crystallites was observed along the step regions of the film during the IBAD portion of deposition. Defect formation in the e-beam ceria layer due to substrate surface relief indicates that “lattice engineering≓ of multilayer epitaxial structures may not be possible when nonplanar surfaces are created during device fabrication. The IBAD CeO₂ layer was more defective than the conformai layer deposited without the impinging ion beam, even in the portions of the film where epitaxy was maintained throughout both layers.     

柯伐镀金盖板电化学腐蚀的剖析及其防腐措施

对半导体器件封装的气密性失效进行了研究。发现，柯伐镀金盖板遭致电化学腐蚀是导致气密性失效的主要原因。对电解液的形成和电化学腐蚀机理进行了深入的分析。提出了防止腐蚀，提高器件气密可靠性的思路和方法。     

Elimination of dislocations in heteroepitaxial MBE and RTCVD Ge x Si1-x grown on patterned Si substrates

We have grown Ge _x Si_1-x (0 <x < 0.20,1000–3000Å thick) on small growth areas etched in the Si substrate. Layers were grown using both molecular beam epitaxy (MBE) at 550° C and rapid thermal chemical vapor deposition (RTCVD) at 900° C. Electron beam induced current images (EBIC) (as well as defect etches and transmission electron microscopy) show that 2800Å-thick, MBE Ge_0.19Si_0.81 on 70-μm-wide mesas have zerothreading and nearly zero misfit dislocations. The Ge_0.19Si{0.81} grown on unpatterned, large areas is heavily dislocated. It is also evident from the images that heterogeneous nucleation of misfit dislocations is dominant in this composition range. 1000Å-thick, RTCVD Ge_0.14Si_0.86 films deposited on 70 μm-wide mesas are also nearly dislocation-free as shown by EBIC, whereas unpatterned areas are more heavily dislocated. Thus, despite the high growth temperatures, only heterogeneous nucleation of misfit dislocations occurs and patterning is still effective. Photoluminescence spectra from arrays of GeSi on Si mesas show that even when the interface dislocation density on the mesas is high, growth on small areas results in a lower dislocation density than growth on large areas.     

A copper/polyimide Metal-base packaging technology

A unique substrate MCPM (Mitsubishi Copper Polyimide Metal-base) technology has been developed by applying our basic copper/polyimide technology.¹ This new substrate technology MCPM is suited for a high-density, multi-layer, multi-chip, high-power module/package, such as used for a computer. The new MCPM was processed using a copper metal base (110 × 110 mm), full copper system (all layers) with 50-μm fine lines. As for pad metallizations for the IC assembly, we evaluated both Ni/Au for chip and wire ICs and solder for TAB ICs. The total number of assembled ICs is 25. To improve the thermal dispersion, copper thermal vias are simultaneously formed by electro-plating. This thermal via is located between the IC chip and copper metal base, and promotes heat dispersion. We employed one large thermal via (4.5 mm^?) and four small vias (1.0 mm^?) for each IC pad. The effect of thermal vias and/or base metal is simulated by a computer analysis and compared with an alumina base substrate. The results show that the thermal vias are effective at lowering the temperature difference between the IC and base substrate, and also lowering the temperature rise of the IC chip. We also evaluated the substrate’s reliability by adhesion test, pressure cooker test, etc.     

多目标多约束的集成电路统计优化策略

对于集成电路设计、生产过程中的多目标、多约束统计优化问题,本文提出了“合格率足够高”的优化宗旨,并从概率论的基本原理出发,结合集成电路的特点,导出了一种合格率的近似表述方法,提出的变权重Monte Carlo法编程简便,效率高。采用这些优化策略设计的集成电路合格率优化系统取得了比较好的结果。     

XPS and AES characterization of hydrolysed γ‐mercaptopropyltrimethoxysilane deposited on Al,Zn and Al–43.4Zn–1.6Si alloy‐coated steel

In this paper Al, Zn and Al–43.4Zn–1.6Si (AlZn) alloy‐coated steel have been treated with the organofunctional silane γ‐mercaptopropyltrimethoxysilane (γ‐MPS). The influence of different metal substrates on the structure and composition of the silane films was investigated with XPS and AES. The films were obtained by dipping the substrates in the silane solution followed by a blow‐dry procedure in nitrogen gas. The results show that the surface concentration of the deposited silane is independent of the metal substrate and that the thickness of the silane film is non‐uniform. The AES measurements indicate that the silane film covers the entire substrate surface and XPS analysis of the silane‐treated substrate surfaces at different take‐off angles indicates that the γ‐MPS molecule is randomly orientated. Also, the results show that the silane is well hydrolysed under the solution conditions used. Finally, in the zinc‐containing silane‐metal systems, i.e. the silane‐treated AlZn and Zn substrates, the results indicate that the γ‐MPS molecules can bond to the substrate surfaces via the thiol group of the molecule. Copyright © 2004 John Wiley & Sons, Ltd.     

Kinetics of thermochemical pretreatment of lignocellulosic materials

The results of an experimental study of the acid hydrolysis of hardwood are presented in the form of values for the three parameters, activation energy, power on the acid concentration, and pre-exponen-tial factor, of the first order kinetic constants for each of the following reaction participants: xylan remaining, glucan remaining, xylose formed, and xylose decomposed. These are used as a base for a quantitative theory to predict the temperature, time, and acid concentrations needed for effective pretreatment of the substrate for subsequent enzymatic hydrolysis of the glucan. This theory is based on the assumption that successful pretreatment requires >90% removal of the xylan, <10% removal of the glucan, and >80% xylose yield. This theory is compared with selected published data.     

New generalized computations of quasi-planar waveguides characteristics

An efficient hybrid field solution to the general multilayer substrates transmission line problems with full shielded and half open cross-sectional geometry is presented by using the waveguide modes coupling and decoupling procedure in the spectral domain. Modal transverse transmission lines corresponding to the LSE and LSM modes are taken into account so that the Green's elements for the edge conditions can be derived by a simple iterative method. In this paper, we analyze not only the propagation constants and characteristic impedances but also the available transmission power capacity and power distribution of most commonly used structures. Normalized eigenmode power levels characterizing the propagation features are computed.