亚硝酰硫酸的离子色谱分析方法研究

建立了离子色谱法(IC)测定亚硝酰硫酸含量的分析方法。考察了亚硝酰硫酸选择性水解生成硝酸和硫酸的条件。亚硝酰硫酸的最佳色谱分析条件为:电导检测器,pH3.5的磷酸二氢钾缓冲溶液作流动相,流速1 mL.min-1,柱温45℃。在优化实验条件下,NO2-、NO3-和SO42-的线性范围分别为2.375~9.515、0.375~1.548、2.051~8.263 mmol.L-1,相关系数均大于0.999 9。样品中NO2-、NO3-和SO24-的加标回收率为99%~101%,其相对标准偏差(RSD)均小于1.0%。通过对各离子含量的测定,用氮平衡法计算出亚硝酰硫酸的含量,相对标准偏差均在0.1%以内。建立的方法与传统的氧化还原滴定法分析亚硝酰硫酸相比,具有分析结果准确、简便快速、成本低的特点,已用于工厂中该产品的质量控制。     

阀切换-离子色谱法测定分析纯硫酸钠中痕量氯离子

建立了阀切换-离子色谱法测定分析纯硫酸钠固体中痕量氯离子含量的方法。ICS-2100离子色谱系统,配置十通阀,用IonPac AS18色谱柱将硫酸钠固体样品中的氯离子和硫酸根离子预分离后,以IonPac TAC-ULP1为富集柱,将氯离子富集后在相同的IonPac AS18色谱柱上进行定量分析。同时以淋洗液发生器产生的不同浓度的KOH作为淋洗液,以抑制型电导检测器测定氯离子的含量。结果表明,阀切换-离子色谱法测定分析纯硫酸钠固体中的痕量氯离子,检出限为10 μg/L,线性相关系数(r2)大于0.999,实际样品的加标回收率为98.0%～103.0%,具有分离度和灵敏度高,选择性好,操作简单等特点。该方法能够准确测定硫酸钠固体中痕量氯离子的含量,适用于高纯化学试剂中痕量氯离子的分离测定。     

一种表面共聚氢氧根选择性阴离子色谱固定相

报道了一种基于聚(苯乙烯-二乙烯基苯)微球(PS-DVB)的表面共聚氢氧根选择性阴离子固定相。它以烯丙基缩水甘油醚(AGE)为功能单体、通过自由基引发直接与PS-DVB微球表面残留的悬挂双键共聚,再通过醇胺开环得到。考察了两种醇胺试剂对分离的影响;扫描电镜、红外光谱、元素分析表征结果表明:表面共聚反应成功在微球表面引入季胺基团,且对微球理化性质无显著影响;所得固定相表现氢氧根淋洗液的高选择性,对常规无机阴离子表现出良好的分离性能(分离度>1.5)和运行稳定性(保留时间的相对标准偏差<1.13%),其实用性通过分析茶叶样品中无机阴离子进行了展示。     

离子色谱法测定电子烟烟液中氨的含量

建立了测定电子烟烟液中的氨含量离子色谱法。样品经10 mol·L-1盐酸溶液萃取10 min后,采用Dionex Ion Pac CS16A阳离子交换柱分离,以MSA为淋洗液进梯度洗脱,用电化学检测器检测。氨的质量浓度在0.05~1.0 mg·L-1范围内与峰面积呈线性关系,检出限(3S/N)为0.035μg·g-1,测定下限(10S/N)为0.12μg·g-1。方法用于12种市售品牌电子烟烟液中氨的测定,加标回收率在93.2%~106%之间,测定值的相对标准偏差(n=5)小于4%。     

应用于802.11a的5.7GHz CMOS LNA设计

使用0.18μm CMOS工艺设计应用于802.11a WLAN的U-NII高频段5.7GHz的LNA.首先选取LNA结构,推导出噪声模型,然后选取在固定功率消耗下最小噪声系数对应的晶体管尺寸,再进行输入输出阻抗匹配和电路调整优化.在使用Bond Wire不加Pad时提供-22.014dB S11,-44.902dB S22,15.063dB S21,-39.44dB S12,2.453dB/2.592dB的噪声系数(NF),-4.1915dBm的三阶互调输入点(IIP3),-15.6dBm的功率1dB压缩点(P1dB)和10mW的功率消耗(Pd).完全考虑Bond Wire和Pad效应的性能参数也已经给出,但噪声系数恶化为3.21/3.23dB,S参数在电路调整优化之后变化不大,整体性能比较突出.     

数字化制造技术

从阐述数字化技术概念出发,综述了国内外数字化制造技术的研究现状,论述了数字化制造技术是先进制造技术的核心技术,并对数字化制造技术的几个核心技术进行了较为详细的介绍,最后对数字化制造技术进行了展望并结合我国实际情况对我国如何发展数字化制造技术提出了几点建议.     

理化实验室规划布局及工程设计

依据理化实验室用房特点,介绍了其必备的功能区域规划布局及基本要求,指出了建设理化实验室的设计思想和遵循原则;并从建筑、结构、装饰、通风空调、给水排水、废水、废液、供配电、气体管道等几个方面探讨了理化实验室的设计方法,可为类似实验室设计和建设提供借鉴.     

Hardware trojans in 3-D ICs due to NBTI effects and countermeasure

Going vertical as in 3-D IC design, reduces the distance between vertical active silicon dies, allowing more dies to be placed closer to each other. However, putting 2-D IC into three-dimensional structure leads to thermal accumulation due to closer proximity of active silicon layers. Also the top die experiences a longer heat dissipation path. All these contribute to higher and non-uniform temperature variations in 3-D IC; higher temperature exacerbates negative bias temperature instability (NBTI). NBTI degrades CMOS transistor parameters such as delay, drain current and threshold voltage. While the impact of transistor aging is well understood from the device point of view, very little is known about its impact on security. We demonstrated that a hardware intruder could leverage this phenomenon to trigger the payload, without requiring a separate triggering circuit. In this paper we provide a detailed analysis on how tiers of 3-D ICs can be subject to exacerbated NBTI. We proposed to embed threshold voltage extractor circuit in conjunction with a novel NBTI-mitigation scheme as a countermeasure against such anticipated Trojans. We validated through post-layout and Monty Carlo simulations using 45 nm technology that our proposed solution against NBTI effects can compensate the NBTI-effects in the 3-D ICs. With the area overhead of 7% implemented in Mod-3 counter, our proposed solution can completely tolerate NBTI-induced degraded threshold voltage shift of up to 60%.     

A comprehensive simulation model for immunity prediction in integrated circuits with respect to substrate injection

This paper presents a comprehensive modelling methodology for the electromagnetic immunity of integrated circuits (ICs) to direct power injection (DPI). The aim of this study is to predict the susceptibility of ICs by the means of simulations performed on an appropriate electrical model of different integrated logic cores located in the same die. These cores are identical from a functional point of view, but differ by their design strategies. The simulation model includes the whole measurement setup as well as the integrated circuit under test, its environment (PCB, power supply) and the substrate model of each logic core. Simulation results and comparisons with measurement results demonstrate the validity of the suggested model. Moreover, they highlight the interest of the aforementioned protection strategies against electromagnetic disturbances.     

Study of Low-Temperature Thermocompression Bonding in Ag-In Solder for Packaging Applications

Low-temperature solders have wide applications in integrated circuits and micro-electromechanical systems packaging. In this article, a study on Ag-In solder for chip-to-chip thermocompression bonding was carried out. The resulting joint consists of AgIn₂ and Ag₉In₄ phases, with the latter phase having a melting temperature higher than 400°C. Complete consumption of In solder into a Ag-rich intermetallic compound is achieved by applying a bond pressure of 1.4 MPa at 180°C for 40 min. We also observe that the bonding pressure effect enables a Ag-rich phase to be formed within a shorter bonding duration (10 min) at a higher pressure of 1.6 MPa. Finally, prolonged aging leads to the formation of the final phase of Ag₉In₄ in the bonded joints.