0. 6 􀀁m CMOS 雷达天线专用控制芯片设计

雷达系统中天线控制电路完成上位机的初始化和扫描角度控制,要求具有高可靠性和低静态电流,用专用集成电路进行设计具有明显优势.采用Verilog HDL语言描述了系统的逻辑功能,超前进位结构的加/减法器提高了电路的工作速度.利用0.6 μm CMOS工艺完成了天线控制电路的物理实现,芯片面积为1.695 mm×1.631 mm.     

军事科研项目中软件项目管理方法研究

列举分析了目前软件开发中存在的问题，提出了在军事科研项目中，对软件项目实施管理的方法，应用先进的软件项目管理理论和方法，有效的提高软件开发效率，确保软件质量。     

第一类永动机幻梦的破灭

介绍了13~18世纪物理学史和科技史上曾名噪一时的第一类永动机的设计方案的破灭.第一类永动机幻梦破灭的历史引起了人们的反思与启示,有力地促进了19世纪中叶能量转化和守恒定律的确立.     

Commuting and stable feedback design for switched linear systems

In the paper, commuting and stable feedback design for switched linear systems is investigated. This problem is formulated as to build up suitable state feedback controller for each subsystem such that the closed-loop systems are not only asymptotically stable but also commuting each other. A new concept, common admissible eigenvector set (CAES), is introduced to establish necessary/sufficient conditions for commuting and stable feedback controllers. For second-order systems, a necessary and sufficient condition is established. Moreover, a parametrization of the CAES is also obtained. The motivation comes from stabilization of switched linear systems which consist of a family of LTI systems and a switching law specifying the switching between them, where if all the subsystems are stable and commuting each other, then the total system is stable under arbitrary switching.     

On c‐Bhaskar Rao designs with block size 4

Several new families of c‐Bhaskar Rao designs with block size 4 are constructed. The necessary conditions for the existence of a c‐BRD (υ,4,λ) are that: (1)λ_min=?λ/3 ≤ c ≤ λ and (2a) c≡λ (mod 2), if υ > 4 or (2b) c≡ λ (mod 4), if υ = 4 or (2c) c≠ λ ? 2, if υ = 5. It is proved that these conditions are necessary, and are sufficient for most pairs of c and λ; in particular, they are sufficient whenever λ?c ≠ 2 for c > 0 and whenever c ? λ_min≠ 2 for c < 0. For c < 0, the necessary conditions are sufficient for υ> 101; for the classic Bhaskar Rao designs, i.e., c = 0, we show the necessary conditions are sufficient with the possible exception of 0‐BRD (υ,4,2)'s for υ≡ 4 (mod 6). © 2002 Wiley Periodicals, Inc. J Combin Designs 10: 361–386, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/jcd.10009     

Constructing Invariant Fairness Measures for Surfaces

The paper proposes a rational method to derive fairness measures for surfaces. It works in cases where isophotes, reflection lines, planar intersection curves, or other curves are used to judge the fairness of the surface. The surface fairness measure is derived by demanding that all the given curves should be fair with respect to an appropriate curve fairness measure. The method is applied to the field of ship hull design where the curves are plane intersections. The method is extended to the case where one considers, not the fairness of one curve, but the fairness of a one parameter family of curves. Six basic third order invariants by which the fairing measures can be expressed are defined. Furthermore, the geometry of a plane intersection curve is studied, and the variation of the total, the normal, and the geodesic curvature and the geodesic torsion is determined.     

现代军用通信设备结构设计新理念

科学技术在不断发展，军用通信设备结构设计的内涵也在不断丰富，时代在不断进步，人们对设备的审美要求越来越高，设计人员应顺应时代发展的潮流，积极吸收、采用新的设计理念。本文详细讨论了有关军用通信设备结构设计新理念的主要内容-创新设计、模块化设计、小型化设计、工业设计和超前设计。     

GALILEO频率结构和信号设计的分析

描述并分析了由欧盟GALILEO信号特别工作组提出的GALILEO全球卫星导航定位系统的频率结构和信号设计。     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

平行机半在线排序问题研究(Ⅰ)

对半在线平行机排序问题的研究进展作了详细综述和进一步探讨。文章给出半在线排序问题的背景、定义、分类和求解。介绍它们定义和在不同机器环境和目标函数下半在线排序问题分类，以及第一类半在线模型的近似算法的设计及其竞争比分析。