HIST: A hierarchical self test methodology for chips,boards, and systems

This article presents the HIST approach, which allows the automated insertion of self test hardware into hierarchically designed circuits and systems to implement the RUNBIST instruction of the IEEE 1149.1 standard. To achieve an optimal and throughout self testable system, the inherent design hierarchy is fully exploited. All chips and boards are provided with appropriate test controllers at each hierarchy level. The approach is able to detect all those faults, which are in the scope of the underlying self test algorithms. In this paper the hierarchical test architecture, the test controllers as well as all necessary synthesis procedures are presented. Finally a successful application of the HIST approach to a cryptography processor is described.     

电子应用产品的防电击试验浅析

本文依据国家有关标准对电子应用产品的防电击试验进行了简介和分析，指出了试验中应注意的问题。     

多项选择题测验信度的一个估计方法及其应用

在多项选择题测验分数等于真实分数和猜测分数之和的假设模型下，本文得到了一个多项选择题测验信度的理论公式，并由此给出了测验信度的估计方法。最后，通过两个例子，说明了本文提出的方法在测验信度分析中的应用，并将这种方法与教育测量中常用的库德——理查逊方法（Ｋｕｄｅｒ－Ｒｉｃｈａｒｄｓｏｎ）进行了比较     

Monitoring Power Dissipation for Fault Detection

In this paper, we suggest that the dynamic power dissipation of acircuit can be used for fault detection. Even those faults which do notaffect static power dissipation can be detected by monitoring dynamic powerdissipation. We discuss how stuck-at, stuck-open, and redundant faults maybe detected by monitoring dynamic power dissipation. In many cases, theFourier spectra of the supply currents in the good and faulty circuits willalso be very different. Further, specific tests can be applied so as toimprove fault coverage. Power monitoring is verified using simulation, andalso experimentally, for example circuits.     

SW233 PIN驱动器自动测试系统的研制

介绍了一种集成电路自动测试系统，该系统采用计算机并口作通信接口，用VB6编程，实现了对外围测试电路的控制，用IEEE-488接口卡控制测试仪器，可对SW233电路的36个参数进行自动测试，并将测试结果自动保存在数据库中。该测试系统具有自动化程度高、操作方便、测试结果精确等特点。     

自体静脉移植血管的拉伸实验研究

本文考察了自体移植静脉的纵向应力应变关系。将狗股静脉移植于股动脉，在术后不同时间切取移植静脉进行纵向单轴拉伸实验。结果表明，移植静脉的应力－应变曲线比正常静脉靠近应力坐标轴并在术后逐渐向左移动。这显示了移植血管管壁组织在术后的逐渐硬化。     

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.     

Testing Extreme Value Conditions

A test statistic is developed that checks the validity of the extreme value conditions without specifiying the shape parameter of the limiting extreme value distribution.     

基于SOC的PAGER控制芯片设计

文章讨论了PAGER控制器芯片（ZQD021）的系统设计，该控制器内部集成了FLASH，SRAM，POCSAG协议解码器和嵌入式MCU CORE。重点分析了芯片的可测性设计（DFT），内嵌FLASH设计，低功耗设计，其设计方法和思路对消费类和嵌入式控制芯片的设计有一定的借鉴意义。     

Synthesis method for testable electrical networks using 1st order building blocks

This work presents a method for synthesizing testable continuous-time linear time-invariant electrical networks using 1st order blocks for the implementation of analog linear circuits. A functional-structural fault model for the block, and a fault dictionary are proposed together with a simple set of test vectors. The method allows, also, the fault grade evaluation for the modeled faults. The results obtained from the two application examples have shown the suitability of the approach as a design for test method for analog circuits.