一种基于方向直方图的嵌入式手势识别系统

将手势识别算法在DSP嵌入式系统上实现,并将算法进行改进使其能适合嵌入式系统的特点,采用改进的边缘像素直方图的方法实现手势识别,最终用Bhattacharyya距离匹配模版,识别手势含义。该方法在嵌入式系统上实现,有实际应用的价值,并对前景的平移和尺寸变化不敏感。算法简单快速,稳健性好,有应用前景。     

一种用于盗版追踪的抗共谋数字指纹方案

目前,数字指纹方案中普遍存在着大用户数下指纹码构造过长以及无法有效追踪盗版者的问题和缺陷。为了解决这些问题,在BS模型的基础上,提出一种卷积扩频两层链接结构的安全指纹构造方法,同时引入备选子码集对维特比译码算法进行了改进,给出了指纹码的译码算法。对构造的指纹进行了性能分析,结果表明,该指纹方案具有更短的码长和更快地盗版者搜索性能。实例证明,该指纹方案能够有效追踪到盗版者及共谋者。     

一种基于DSP的低复杂度DTMB数字电视接收机的频域均衡器

基于DSP的数字电视接收机,具有低成本和低复杂度的优点,是未来数字电视接收机的发展方向。然而,基于DSP的数字电视频域均衡,需要大量的复数除法,给接收机的实现带来了巨大的困难。本文提出了一种基于DSP的低复杂度的、兼容单、多载波的DTMB接收机频域均衡器。本文的频域均衡器先将复数除法转换为实数除法,再对除数进行PCM A-Law和-Law压缩编码,然后以压缩编码后的码字作为索引进行查表,得到除数的倒数,最后通过乘法实现频域均衡器。仿真结果表明,本文的基于DSP的频域均衡方法,存储空间较少,消耗的指令周期数较少,运算速度快,同时性能较高。     

BitTorrent在嵌入式系统中的应用

开发具有低功耗、微内核、体积小,并且具有下载功能的嵌入式系统,是非常具有商业价值的。BitTorrent系统是P2P文件共享技术中应用较为广泛的一种,本文在分析通用的BitTorrent软件基础上,给出一种适合嵌入式系统的BitTorrent下载模型,并通过编码在嵌入式Linux之上实现了稳定快速的下载。     

Modern development methods and tools for embedded reconfigurable systems: A survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.     

基于嵌入式技术的靶场破片测速系统设计

为了增强靶场破片测速系统的便携性和实时性,提出了一种基于嵌入式技术的靶场破片测速系统设计方法。系统硬件上采用ARM＋FPGA的架构,软件上不仅采用Qt／Embedded设计了图形界面,而且给出了嵌入式设备上Qt／Embedded程序的优化方法。经过多次野外破片测速试验检测,系统工作稳定,可实现破片飞行速度、速度降、末速度、破片速度分布等参数的获取。试验结果证明,系统能够满足靶场破片测速的大多数需要。     

Layered Access Control Schemes on Watermarked Scalable Media

Intellectual Property (IP) protection is a critical element in multimedia transmission and delivery systems. Conventional IP protection on multimedia data can be categorized into encryption and watermarking. In this paper, a structure to perform layered access control on scalable media by combining encryption and robust watermarking is proposed, implemented, and verified. By taking advantages of the nature of both encryption and watermarking, copyrights of multimedia contents can be well protected and at the same time, multiple-grade services can be provided. In the summated examples, we assume a scalable transmission scheme over the broadcasting environment and use it to test the effectiveness of proposed method. When the embedded watermark is extracted with high confidence, the key to decrypt the next layer can be perfectly recovered. Then, the media contents are reconstructed and the copyrights are assured. The application examples also demonstrate the practicality of the proposed system.

基于动态交互数值组件的设计与实现

在嵌入式程序设计中,需要使用数值表达式计算数值组件,以解决动态交互的数值计算问题,介绍了一种通过对数值表达式进行解释和计算来设计和实现数值组件。     

一种高效的基于矢量量化的彩色视频图像压缩编码方法

针对彩色视频图像提出了一种DCT域内基于矢量量化的高效编码方法。为去掉彩色图像各分量间的相关性,首先将图像由RGB空间转换到YUV空间,然后根据人类视觉特征（HVS）对色度信号U、V进行了亚采样和平均化处理;对亮度信号Y则进行分块DCT变换,并根据HVS特征对变化域内的块矢量进行自适应分类,然后根据矢量的类型分别构造码矢和进行全局码书设计。提出的全局码书设计方案可以根据帧间相关性及码字使用频率,对码书的内容自动进行更新和替换,以适应场景内容的变化。实验结果表明：在保证图像重建质量的前提下,本文提出的方法具有较高的压缩效率,比较适合于视频会议以及水下视频观测等应用场合。     

Improved macroblock level rate control for the spatially scalable extension of H.264/AVC

An improved rate control algorithm, designed for scalable video coders incorporating interlayer prediction, is proposed. Firstly, a Rate Distortion (RD) model for interlayer prediction involving the spatial enhancement layers is devised. An optimised Mean Absolute Difference (MAD) prediction model for the spatial enhancement layers that considers both the MAD from the spatial base layer in the same frame and the MAD from the corresponding macroblock in previous frames is also proposed. Simulation results show that the resulting algorithm produces accurate rate control with an average bit rate error of less than 0.26%. Compared with the JVT-W043 default rate control algorithm of the JSVM, the proposed algorithm improves the average PSNR by up to 0.53 dB or reduces the bit rate by an average of 10.95%. Furthermore, the proposed algorithm can be combined with the existing rate control scheme for H.264/AVC, resulting in further improvements.