方波调制误差对光纤陀螺的影响分析与实验

根据数字闭环光纤陀螺的方波调制、解调原理,指出调制方波的频率、相位和占空比不理想是造成方波调制误差的原因。讨论了周期脉冲干扰的频率和相位特征,利用周期脉冲干扰的傅里叶级数推导出了方波调制误差的数学模型。建立了带有方波调制误差的闭环光纤陀螺简化模型,推导出了方波调制误差和陀螺输出偏置误差的关系。通过仿真和测试分析了调制方波的周期、相位、占空比、光纤环的群延时以及放大电路的增益带宽对陀螺输出偏置的影响。最后,给出了一种利用周期脉冲干扰波形检测方波调制误差的简易方法。     

数模混合的可调占空比电路RC2053

本文介绍了车用交流稳压调节电路RC2053的工作原理，较详细地介绍了实现脉宽调制的方法，并结合时序图给出了电路的实际工作模式。     

一种高速高精度时钟占空比稳定电路

设计了一种高速高精度的时钟占空比稳定电路。采用全差分连续时间积分器将时钟占空比量化为电压信号,积分器对占空比偏差的累积效应可使电路达到很高的调整精度。采用跨导运算放大器将电压信号转换为电流信号,并加载到输入时钟缓冲器上,改变其输出时钟的直流电平,从而调整输出时钟的占空比,避免了调整输出时钟上升/下降沿带来的较大抖动。采用TSMC 0.18 μm CMOS工艺进行设计,电源电压为2 V。当输入差分时钟频率为1.6 GHz时,可以将占空比范围为20%~80%的输入时钟信号的占空比均调节至(50±0.5)%,且输出时钟抖动小于159.398 fs,适用于超高速的信号处理系统。     

一种可实现宽范围电压输出的DC-DC变换器设计

提出了一种实用的可实现宽范围电压输出的平方型变换器,分析了该变换器工作原理,对主电路中的功率管、变压器、二极管、输出电容和输出电感等参数进行了设计。根据设计的结果,制作了变换器,并利用示波器采集了该变换器样机重要元器件的工作波形;对样机效率进行考察,全负荷工作效率在80%以上,占空比最大为0.65,验证了设计的正确性。     

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采用由脉冲负偏压调节的等离子体增强化学气相沉积方法,以硅烷为源气体,在玻璃基片上沉积得到了多孔二氧化硅薄膜。将反应过程中加在沉积区域的脉冲偏压固定在-350V,当占空比从0.162增大到0.864时,薄膜样品的形貌、成份和结构均不相同。扫描电镜照片表明,组成多孔氧化硅薄膜的颗粒在占空比增大时变得细腻,并且薄膜整体变得多孔且蓬松。拉曼光谱和红外光谱结果显示,薄膜样品中的非晶硅和Si-H键在较高的占空比下减弱甚至消失。占空比升高时氧化硅桥键所占比例持续增加。     

泵浦用高平均功率二极管激光器研制

针对高平均功率线阵二极管激光器(DL )芯片的工作要求,开展了相应的封装结构设计和高效冷却技术研究.封装的单条线阵DL连续输出激光功率50 W,工作寿命达到5 000 h,10%占空比准连续输出激光脉冲功率150 W,25%占空比准连续输出激光脉冲功率100 W,工作寿命达到5×109次脉冲.采用模块式封装方式由25个模块堆叠,制作出了连续激光功率1 kW和20%占空比工作脉冲功率2.5 kW的叠阵二极管激光器.     

Study on the discrete dielectrophoresis for particle–cell separation

This paper presents the application of the discrete dielectrophoretic force to separate polystyrene particles from red blood cells. The separation process employs a simple microfluidic device that is composed of interdigitated electrodes and a microchannel. The discrete dielectrophoretic force is generated by adjusting the duty cycle of the applied voltage. The electrodes make a tilt angle with the microchannel to change the moving direction of the red blood cells. By adjusting the voltage magnitude and duty cycle, we investigate the deflection of red blood cells and the variation of cell velocity along electrode edge under positive dielectrophoresis. The experiments with polystyrene particles show that the enrichment of the particles is greater than 150 times. The maximum separation efficiency is 97% for particle-to-cell number ratio equal to 1:2000 in the sample having high cell concentration. Using the appropriate applied voltage magnitude and duty cycle, the discrete dielectrophoretic force can prevent the clogging of microchannel while successfully separating the particles from the cells with high enrichment and efficiency. The proposed principle can be readily applied to dielectrophoresis-based devices for biomedical sample preparation or diagnosis such as the separation of rare or infected cells from a blood sample.     

Electromigration subjected to Joule heating under pulsed DC stress

This article reports an electromigration-lifetime model that incorporates the effect of Joule heating under pulsed DC condition. This median-time-to-failure model accounts for applied current density, duty factor, frequency, thermal time constant, and interconnect geometry. The model predictions reported in this work agree very well with numerical simulation and experimental data over a wide range of current densities and frequencies.     

用于ICF驱动器的分频光栅两种工艺误差分析

 对用于ICF驱动器分频光栅的刻槽深度进行了优化，使其具有更优的分频效果。在此基础上，对制作工艺带来的占空比误差和塌边结构进行了分析，给出了分频光栅具有良好分频效果时工艺上所能允许的误差范围。     

A synthesizable pseudo fractional-N clock generator with improved duty cycle output

A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle output is presented by the pseudo fractional-N frequency synthesizer unit for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated by following the design flowchart. It has been fabricated in a 0.13 μm CMOS technology and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed synthesizable pseudo fractional-N clock generator is from 12.5 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rate of the output clock frequency is 1.5% and the measured power dissipation of the pseudo fractional-N frequency synthesizer unit is 146 μW at 304 MHz.