基于FPGA技术的DRAM分时存取方法

介绍了一种基于现场可编程技术对DRAM进行读写和刷新操作的方法，根据现场可编程器件设计的特点，结合DRAM读写和刷新时序的要求，提出了同步化操作DRAM的思想，给出了具体同步化操作DRAM的实现方法，针对现场可编程器件设计中经常有多模块同时存取DRAM芯片的需求，提出了对DRAM芯片进行分时存取的方法，讨论了该方法的实现机制，结合具体的项目设计，给出了分时存取方法的关键时序，避开了复杂的DRAM控制器，节省了设计资源，简单方便地解决了DRAM操作的仲裁问题。     

Optimization of process conditions for the formation of hemispherical-grained (HSG) silicon in high-density DRAM capacitor

We have compared the capacitances of a conventional stacked capacitor and hemispherical-grained silicon (HSG-Si), in which the seeding method was applied to storage electrode of 64 Mbit dynamic random access memory (DRAM) through Si₂H₆-molecule irradiation and annealing for HSG-Si formation. Also, we considered the variation of the HSG-Si thickness due to the phosphorus concentration of storage poly-silicon in process condition and the effect of its thickness on the cell capacitance and failure occurrence, etc. We investigated the effect of the deposition temperature of amorphous poly-silicon on the HSG-Si formation. As a result, the optimum process conditions of the phosphorus concentration, the deposition temperature of storage poly-silicon and the HSG thickness in HSG formation are 3.5–4.5×10¹⁹ atoms/cm³, 530°C and 450 Å, respectively. It is found that the limit thickness of dielectric film of 64 Mbit DRAM capacitor according to the optimized process condition is 65 Å.     

一种高速增益单元存储器的内建自测试方案

介绍了一种用于测试高速增益单元嵌入式动态随机存储器的内建自测试方案。该方案包括了指令集设计和体系结构设计。四级指令流水线的引入使全速测试成为可能。该设计方案可以通过执行不同的测试指令,对待测存储器执行多种类型的测试,从而达到较高的故障覆盖率。该内建自测试模块被集成在了一个存储容量为8kb的增益单元嵌入式动态随机存储器芯片中,并在中芯国际0.13μm标准逻辑工艺下进行了流片验证。芯片测试结果表明,该内建自测试方案可以在多种测试模式下对待测存储器执行全速测试,提高了测试速度,降低了对自动测试设备的性能要求,提高了测试的效率。     

用于TFT-LCD驱动芯片的内置DRAM设计

TFT-LCD驱动芯片中需要较大容量的内置存储器,相对于静态存储电路而言,动态存储电路节省了芯片的面积,有利于芯片成本的降低.文章讨论了用于TFT-LCD驱动芯片内置DRAM的分块设计方法,结合芯片物理特点将其分为左右对称两块.采用改进的3-T结构DRAM存储阵列,省去了伪存储单元,节省了面积,降低了功耗.优化了DRAM的刷新电路,省略了判断信号与RAS和CAS先后顺序的仲裁电路.结合芯片本身的特点设计了行、列译码电路.对于芯片的仿真,采用了模拟验证和形式验证相结合的前端设计验证方法,同时又采用了结构化抽取寄生参数和建立关键路径的后仿真.     

The investigation of DARC etch back in DRAM capacitor oxide mask opening

Opening the silicon oxide mask of a capacitor in dynamic random access memory is a critical process on a capacitive coupled plasma (CCP) etch tool.Three steps,dielectric anti-reflective coating (DARC) etch back,silicon oxide etch and strip,are contained.To acquire good performance,such as low leakage current and high capacitance,for further fabricating capacitors,we should firstly optimize DARC etch back.We developed some experiments,focusing on etch time and chemistry,to evalu-ate the profile of a silicon oxide mask,DARC remain and critical dimension.The result shows that etch back time should be con-trolled in the range from 50 to 60 s,based on the current equipment and condition.It will make B/T ratio higher than 70％ mean-while resolve the DARC remain issue.We also found that CH2F2 flow should be ～15 sccm to avoid reversed CD trend and keep in-line CD.     

基于傅里叶变换红外反射谱的DRAM深沟槽结构测量系统研究

提出了一种基于傅里叶变换红外(FTIR)反射谱的动态随机存储器(DRAM)深沟槽结构测量方法与系统。给出了测量原理与方法,设计了测量系统光路。通过可变光阑调节探测光斑大小并选择合适的入射角,消除了背面杂散光反射干扰的影响,大大提高了信噪比。对DRAM深沟槽样品进行反射光谱图测试与实验研究,表明所述方法与系统能够提取出纳米级精度的深沟槽参数。该技术提供了一种无接触、非破坏、快速、低成本和高精度的深沟槽结构测量新途径,在集成电路制造过程中的在线监测与工艺控制方面具有广阔的应用前景。     

New TIT capacitor with ZrO2/Al2O3/ZrO2 dielectrics for 60 nm and below DRAMs

New ZrO₂/Al₂O₃/ZrO₂ (ZAZ) dielectric film was successfully developed for DRAM capacitor dielectrics of 60 nm and below technologies. ZAZ dielectric film grown by ALD has a mixture structure of crystalline phase ZrO₂ and amorphous phase Al₂O₃ in order to optimize dielectric properties. ZAZ TIT capacitor showed small Tox.eq of 8.5 Å and a low leakage current density of 0.35 fA/cell, which meet leakage current criteria of 0.5 fA/cell for mass production. ZAZ TIT capacitor showed a smaller cap leak fail bit than HAH capacitor and stable leakage current up to 550 °C anneal. TDDB (time dependent dielectric breakdown) behavior reliably satisfied the 10-year lifetime criteria within operation voltage range.     

Can molecular resonant tunneling diodes be used for local refresh of DRAM memory cells?

The requirements of resonant tunneling diodes (RTDs) in general and molecular diodes in particular for use as local refresh in low-power DRAM memory cells are discussed. Simulations show that none of the so far published molecules showing negative differential resistance have adequate electrical properties. Further, simulations show that present RTDs in III–V materials or SiGe are not compatible with the demands of future DRAM generations. A detailed list of requirements on the electrical properties of molecular RTDs or RTDs made of nanocrystals is presented. For instance, the valley current of the RTDs should be in the 10⁻¹⁶ A range. The issues of acceptable differences in the number of active molecules constituting the two RTDs, and the maximum acceptable contact resistance between the molecules and the silicon substrate are addressed.     

A new extension method of retention time for memory cell on dynamic random access memory

Demands have been placed on dynamic random access memory (DRAM) to not only increase memory capacity and data transfer speed but also to reduce operating and standby currents. When a system uses DRAM, the restricted data retention time necessitates a refresh operation because each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to memory capacity. A new method is proposed to reduce the refresh power consumption dynamically, when full memory capacity is not required, by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation of retention times among memory cells. The proposed method reduces the frequency of disturbance and power consumption by two orders of magnitude. Furthermore, the conversion itself can be realized very simply from the structure of the DRAM array circuit, while maintaining all conventional functions and operations in the full array access mode.     

适用于深沟槽结构观测的TEM样品制备技术

对于深沟槽DRAM电容这类纵向深度深(超过5μm)但是平面尺寸又很小(小于0.2μm×0.2μm)的结构来说,传统的TEM制样方法,无法满足其细微结构全面观测的需求,此外传统的方法制样也比较费时,成功率也比较低。介绍了一种FIB横向切割技术,适用于对这类结构的观测。它与传统FIB制样方法的主要区别在于,切割方向由纵向切割改为横向切割。用这种方法制备的TEM样品,可以完整地观测同一个深沟槽DRAM电容结构的所有细微结构。制样过程比较简单、速度快、成功率高。以一个实例分析、比较了传统制样方法和新的制样方法,突显了FIB横向切割技术的优点。