用于Gb级DRAM的TiO2薄膜结构的研究

运用反应磁控溅技术制备了应用于Ｇｂ级ＤＲＡＭ中的ＴｉＯ２薄膜。本文报道了对该薄膜进行Ｘ射线衍射结构分析所得到的详细结果，并给出了薄膜结构同热处理条件之间的关系。     

Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of 3.63 µm². We designed a 1Mb DRAM with an open bit‐line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when V_cc is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.     

Designing an Embedded Video Processing Camera Using a 16-bit Microprocessor for a Surveillance System

This paper describes the design and implementation of a hybrid intelligent surveillance system that consists of an embedded system and a personal computer (PC)-based system. The embedded system performs some of the image processing tasks and sends the processed data to the PC. The PC tracks persons and recognizes two-person interactions by using a grayscale side view image sequence captured by a stationary camera. Based on our previous research, we explored the optimum division of tasks between the embedded system and the PC, simulated the embedded system using dataflow models in Ptolemy, and prototyped the embedded system in real-time hardware and software using a 16-bit CISC microprocessor. This embedded system processes one 320 × 240 frame in 89 ms, which yields one-third of the rate of 30 Hz video system. In addition, the real-time embedded system prototype uses 5.7 K bytes of program memory, 854 K bytes of internal data memory and 2 M bytes external DRAM. Koichi Sato is a Ph.D. student in the Department of Electrical and Computer Engineering at The University of Texas at Austin. He earned his B.S. in University of Tokyo, Japan in 1993. He worked for Automotive Development Center in Mitsubishi Electric Corporation where he was involved in lane and automobile recognition in vehicle video processing products such as automatic cruise control and drowsiness detection systems. He enrolled in the current University at 1998 and received an M.S in 2000. In his Master's thesis he worked on human tracking and human interaction recognition. His current work includes velocity extraction using the TSV transform, object tracking, and 3D object reconstruction. Brian L. Evans is a tenured Associate Professor in the Department of Electrical and Computer Engineering at The University of Texas at Austin. His research and teaching efforts are in embedded real-time signal and image processing systems. In signal processing, his research group is focused on the design and real-time software implementation of ADSL and VDSL transceivers, for high-speed Internet access. In image processing, his group is focused on the design and real-time software implementation of high-quality halftoning for desktop printers, smart image acquisition for digital still cameras, and 3-D sonar imaging systems. In signal and image processing, Dr. Evans has published over 100 refereed conference and journal papers. Dr. Evans is the primary architect of the Signals and Systems Pack for Mathematica, which has been on the market since October 1995. He was a key contributor to UC Berkeley's Ptolemy Classic electronic design automation environment for embedded systems, which has been successfully commercialized by Agilent and Cadence. His BSEECS (1987) degree is from the Rose-Hulman Institute of Technology, and his MSEE (1988) and PhDEE (1993) degrees are from the Georgia Institute of Technology. From 1993 to 1996, he was a post-doctoral researcher in the Ptolemy project at UC Berkeley. He is a member of the Design and Implementation of Signal Processing Systems Technical Committee of the IEEE Signal Processing Society, and a Senior Member of the IEEE. He is the recipient of a 1997 National Science Foundation CAREER Award. J.K. Aggarwal has served on the faculty of The University of Texas at Austin College of Engineering since 1964 and is currently Cullen Professor of Electrical and Computer Engineering and Director of the Computer and Vision Research Center. His research interests include computer vision and pattern recognition focusing on human motion. A Fellow of IEEE since 1976 and IAPR since 1998, he received the Senior Research Award of the American Society of Engineering Education in 1992, the 1996 Technical Achievement Award of the IEEE Computer Society and the graduate teaching award at The University of Texas at Austin in 1992. He has served as Chairman of the IEEE Computer Society Technical Committee on Pattern Analysis and Machine Intelligence (1987--1989); Director of the NATO Advanced Research Workshop on Multisensor Fusion for Computer Vision, Grenoble, France (1989); Chairman of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition (1993), and President of the International Association for Pattern Recognition (1992--1994). He is a Life Fellow of IEEE and Golden Core member of IEEE Computer Society. He has authored and edited a number of books, chapters, proceedings of conferences, and papers.     

CS8831CN测试方法

CS8 8 31CN是用于语音录放的单片CMOSLSI,采用ADM (自适应增量调制 )。它与动态RAM以及包括话筒、扬声器、放大器等的音频电路共同构成一个完整的语音录放系统。     

Characteristics of PECVD grown tungsten nitride films as diffusion barrier layers for ULSI DRAM applications

We have developed tungsten nitride (W-Nitride) films grown by plasma enhanced chemical vapor deposition (PECVD) for barrier material applications in ultra large scale integration DRAM devices. As-deposited W-Nitride films show an amorphous structure, which transforms into crystalline, β-W₂N and α-W phases upon annealing at 800°C. The resistivity of the as-deposited films grown at the NH₃/WF₆ gas flow ratio of 1 is about 160 μω-cm, which decreases to 50 μω-cm after an rapid thermal annealing treatment at 800°C. In the contact holes with the size of 0.35 μm and aspect ratio of 3.5, the bottom step coverage of the tungsten nitride films is about 60%, which is about three times higher than that of collimated-TiN films. We obtained contact resistance and leakage current with the tungsten nitride barrier layer comparable to those with conventional collimated TiN films. The contact resistance and leakage current are stable upon thermal stressing at 450°C up to 48 h.     

图文电视中大容量数字存储器的设计

介绍了图文电视中大容量数字存储器设计的基本思想和系统框图,给出了ＤＲＡＭ控制电路和字符控制电路的设计方案。     

用FPGA实现图文电视中汉字显示系统

简要介绍了图文电视的基本概念,详细描述了接收端大容量数字存储器的基本设计思想,其中包括单片机控制系统和两个ＦＰＧＡ功能模块的具体实现,本设计达到了预期的功能。     

适用于深沟槽结构观测的TEM样品制备技术

对于深沟槽DRAM电容这类纵向深度深(超过5μm)但是平面尺寸又很小(小于0.2μm×0.2μm)的结构来说,传统的TEM制样方法,无法满足其细微结构全面观测的需求,此外传统的方法制样也比较费时,成功率也比较低。介绍了一种FIB横向切割技术,适用于对这类结构的观测。它与传统FIB制样方法的主要区别在于,切割方向由纵向切割改为横向切割。用这种方法制备的TEM样品,可以完整地观测同一个深沟槽DRAM电容结构的所有细微结构。制样过程比较简单、速度快、成功率高。以一个实例分析、比较了传统制样方法和新的制样方法,突显了FIB横向切割技术的优点。     

An 80% larger-current-output negative CMOS charge pump with 10% area penalty for sub-1-V-VCC negative-word-line DRAMs

A new CMOS negative charge pump scheme is proposed in this paper. This new pump scheme can generate output current which is 80% larger than the conventional pump with the sacrificial 10% area penalty. This new pump is regarded to be suitable to sub-1-V-V_CC DRAMs with the negative-word-line (NWL) scheme, where the dynamic current consumption is expected to be very large.     

内存条的结构与应用研究

采用大容量的存储器扩大单片机数据空间，常用的器件有：RAM、FLASH RAM、NVRAM以及DRAM。其中，DRAM具有容量特点大、价格低的优点。介绍了内存条的刷新原理和工作时序，详细讨论了89C51单片机与内存条接口设计的方法。最后采用ispLSI1032进行了集成处理，简单可靠，可使单片机系统拥有大容量的数据存储空间。