一种四通道PMC宽带数字接收机的设计与实现

介绍了一种通用宽带四通道数字接收机PMC背板的设计与实现.该设计用ADI公司的AD6645(14 bit,80 Msam-pie·s-1/105 Msample·s-1)作为模数转换器件,采用专用DDC芯片ISL5416和StratixⅡ系列的FPGA级联的结构,用PCI9656作为PCI接口芯片,板卡为标准PMC板型.文中给出了板卡的原理结构和性能指标的测试结果等.实践表明,该数字接收机具有精度高、使用灵活、处理和互联能力强等优点.     

一种用晶闸管实现的大功率电流型逆变电路

本文介绍了一种带有辅助晶闸管换相式电流型逆变电路,重点分析了其工作原理及换相电容、换相电感的选取,给出了试验波形.该电路已在工业中得到应用.     

甚长基线干涉测量数字基带转换器子通道时延影响分析

为提高甚长基线干涉测量(VLBI)带宽综合处理精度,在接收系统各通道时延一致的情况下,对数字基带转换器(DBBC)子通道时延对带宽综合精度的影响进行了分析。通过理论推导,首次发现在单站群时延测量中,子通道时延会使不同子通道之间产生相位阶梯,引入带宽综合处理误差;在双站时延差测量中,当两个观测站相应子通道本振频率差不相同时,也会出现相位阶梯,降低带宽综合处理精度。针对不同数字基带转换器结构,讨论子通道时延的影响域,提出通过子通道时延补偿消除相位阶梯。仿真结果表明,子通道时延补偿可以有效消除相位阶梯,使带宽综合处理精度至少提高一个量级以上。     

DPL-based novel time equalized CMOS ternary-to-binary converter

ABSTRACT

Radix-3 (Ternary) logic has been receiving renewed attention as a feasible alternative to conventional Radix-2 system in processor-design and multi-valued logic-design due to computational-ease, speed and reduced interconnect. Yet the real world is binary. Thus to harvest the benefits, the ternary-processing stage must be appended with a ternary-to-binary converter. This work introduces a novel 3-step-strategy to convert Ternary-input into Binary-output. Proposed single-supply, Double-Pass-Transistor-Logic (DPL) Ternary-to-Binary-Converter (TBC) is designed with normal-process Enhancement-type-Metal-Oxide-Semiconductor- Field-Effect-Transistor (E-MOSFET) and wave-pipelined through coarse and fine tuning to achieve faster response with reduced power-dissipation and fabrication-cost/complexity. Data-independent propagation delay in DPL is exploited here to achieve efficient time-equalisation. The TBC is designed, optimised, validated and evaluated on TSMC 180nm Single-Poly-Double-Metal (SPDM) CMOS-process on 1.8V supply-rail at 25°C temperature using Tanner EDA V.13. Ternary values are encoded with 1.8, 0.9 and 0V to represent Ternary-digits (‘trit’s) ‘2’, ‘1’ and ‘0’, respectively. T-Spice post-layout-simulation shows the proposed 2:4 TBC consumes 177.74 μW power operating at 500 Mega-trit-per-second (Mtps) and takes 0.72 ns to convert. To address reliability issue, the corner analysis with TT (Typical), SS (Slow) and FF (Fast) PVT-variation is performed and worst case responses are recorded which are observed to be within acceptable-limit.     

一种全功率风力发电变流器关键技术研究

风力发电机类型很多,本文选择了几种风力发电系统的结构进行了对比,给出了一种不控整流器加BOOST升压加PWM逆变的全功率风力发电变流器的原理、设计中采用的关键技术及试验结果。     

基于TL494的双向DC-DC变换器设计

针对电池组的充放电实际需求,提出了以TL494为核心的双向DC-DC变换器方案。充电用同步Buck拓扑结构和步进可调的恒流充电模式,实时监测充电电流和充放电电压的大小,具有过充保护和过压消失后自动恢复的能力。放电用同步Boost拓扑结构,对负载恒流供电。充电电流在1~2A范围内步进可调,步进值不大于0.1A,电流控制准确度不低于5%,变化率不大于1%,变换器的效率为92.29%,准确度不低于3.9%。放电模式,输出电压保持30±0.5V,变换器效率90.19%。整个设计样机重量仅为440g,具有一定的实际应用价值。     

一种新型基于二次型Buck变换器的交错并联LED驱动电源

为了减小输出电流纹波,提出了一种基于二次型Buck变换器的交错并联LED驱动电源。主电路由一个二次型Buck变换器和一条新增支路构成,这条新增支路包括一个开关管、二极管、电感和电容,优化了原有的拓扑结构,实现了高功率因数和恒流输出。采用交错并联技术,有效减小了滤波电感和输出电流纹波,纹波大小仅为输出电流峰峰值的0.18%。最后通过实验样机详细验证了理论分析的正确性。     

Digital background calibration of capacitor mismatches and harmonic distortion in pipelined ADC

A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.     

单端正激变换器混合离散优化设计

本文讨论了四路输出单端正激变换器功率变换级的优化设计方法,给出了优化数学模型。其优化设计方法能直接用于工程设计。文中给出了一个实例及计算结果。     

基于CAN总线的变频设备远程监控系统的实现

本文详细介绍了利用CAN总线实现对变频设备系统的远程集中监测和控制策略。