Some new results on superimposed codes

A (w,r) cover‐free family is a family of subsets of a finite set such that no intersection of w members of the family is covered by a union of r others. A (w,r) superimposed code is the incidence matrix of such a family. Such a family also arises in cryptography as the concept of key distribution pattern. In the present paper, we give some new results on superimposed codes. First we construct superimposed codes from super‐simple designs which give us results better than superimposed codes constructed by other known methods. Next we prove the uniqueness of the (1,2) superimposed code of size 9 × 12, the (2,2) superimposed code of size 14 × 8, and the (2,3) superimposed code of size 30 × 10. Finally, we improve numerical values of upper bounds for the asymptotic rate of some (w,r) superimposed codes. © 2004 Wiley Periodicals, Inc.     

Comparison of two models for managing reliability growth during product design

Relying on reliability growth testing to improve system designis neither usually effective nor efficient. Instead it is importantto design in reliability. This requires models to estimate reliabilitygrowth in the design that can be used to assess whether goalreliability will be achieved within the target timescale forthe design process. Many models have been developed for analysisof reliability growth on test, but there has been much lessattention given to reliability growth in design. This paperdescribes and compares two models: one motivated by the practicalengineering process; the other by extending the reasoning ofstatistical reliability growth modelling. Both models are referencedin the recently revised edition of international standard IEC61164. However, there has been no reported evaluation of theirproperties. Therefore, this paper explores the commonalitiesand differences between these models through an assessment oftheir logic and their application to an industrial example.Recommendations are given for the use of reliability growthmodels to aid management of the design process and to informproduct development.     

基于Protel DXP的电路仿真设计

Protel DXP是集所有设计工具于一身的电子设计自动化(EDA)软件.文中运用其内嵌的仿真器叙述了分压式偏置电路放大器的仿真设计过程,设计过程简单、方便.在电子线路理论教学过程中引入电路设计仿真环节在不同情况下对电路进行实时分析,不仅可以提高学生的学习兴趣,而且能够在较短时间内加深学生对理论知识的理解;在工程设计过程中利用仿真工具对电路进行即时测试,可以缩短设计周期,提高设计效率.     

Order restricted randomized designs for control versus treatment comparison

We develop a method of randomizing units to treatments that relies on subjective judgement or on possible coarse modeling to produce restrictions on the randomization. The procedure thus fits within the general framework of ranked set sampling. However, instead of selecting a single unit from each set for full measurement, all units within a set are used. The units within a set are assigned to different treatments. Such an assignment translates the positive dependence among units within a set into a reduction in variation of contrasting features of the treatments. A test for treatment versus control comparison, with controlled familywise error rate, is developed along with the associated confidence intervals. The new procedure is shown to be superior to corresponding procedures based on completely randomized or ranked set sample designs. The superiority appears both in asymptotic relative efficiency and in power for finite sample sizes. Importantly, this test does not rely on perfect rankings; rather, the information in the data on the quality of rankings is exploited to maintain the level of the test when rankings are imperfect. The asymptotic relative efficiency of the test is not affected by estimation of the quality of rankings, and the finite sample performance is only mildly affected.     

二元液态金属Cu-Ni和Ag-Cu凝固过程的分子动力学模拟研究

用Quantum Sutton-Chen多体势对Ag6Cu4和CuNi液态金属凝固过程进行了分子动力学模拟研究.在冷却速率2×1012到2×1014K/s范围内,CuNi总是形成fcc晶体结构,而Ag6Cu4总是形成非晶态结构.考虑到CuNi及AgCu中原子半径之比分别为1.025和1.13,那么模拟结果证实了原子的尺寸差别是非晶态合金形成的一个主要影响因素.此外采用键对及原子多面体类型指数法对凝固过程中微观结构组态变化的分析,不但能说明二十面体结构在非晶态合金形成和稳定性中所起的关键作用,又有助于对液态金属的凝固过程、非晶态结构特征的深入理解.     

32位MIPS微处理器中乘法器的设计和实现

在Booth算法的基础上,结合MIPS 4KC微处理器中的流水线结构和乘法器的工作过程,提出了一种改进的Booth乘法器的设计方法,并采用全制定方法实现,用这种方法实现的乘法器单元具有面积小、单元电路可重复性好、版图设计工作量小、功耗低等特点.     

SoC低功耗设计中的DVS技术

随着系统芯片(SoC)集成更多的功能并采用更先进的工艺,它所面临的高性能与低功耗的矛盾越来越突出.动态电压调整(DVS)技术可以在不影响处理器性能的前提下,通过性能预测软件根据处理器的繁忙程度调整处理器的工作电压和工作频率,达到降低芯片功耗的目的.文中讨论了DVS技术降低功耗的可能性,介绍了如何利用两种不同的DVS技术让处理器根据当前的工作负荷运行在不同的性能水平上,以节省不必要的功耗.     

提高塑封双列直插式光耦合器绝缘耐压的设计和工艺要点

介绍了研制出其性能达国际先进公司同类产品水平的塑封双列直插式光耦合器的工作原理和提高绝缘耐压的技术难点，从引线框架设计、加工精度控制、内包封材料选型、理想内包封形状控制、塑封气密性的实现、环境条件的完善等方面讨论了提高绝缘耐压的设计和工艺要点。     

一种低功耗Cache设计技术的研究

低功耗、高性能的cache系统设计是嵌入式DSP芯片设计的关键。本文在多媒体处理DSP芯片MD32的设计实践中，提出一种利用读／写缓冲器作为零级cache，减少对数据、指令cache的读／写次数，由于缓冲器读取功耗远远小于片上cache，从而减小cache相关功耗的方法。通过多种多媒体处理测试程序的验证，该技术可减少对指令cache或者数据cache20％～40％的读取次数，以较小芯片面积的增加换取了较大的功耗降低。     

IPv6和基于IPv6的网络设计

对IPv6协议的主要内容进行了简要介绍,并针对IPv6的特点对基于IPv6的网络设计进行了探讨。