MASH ΣΔ modulators with a noise-shaped two-step ADC in the second stage

In this paper, a multi-stage noise-shaping (MASH) sigma-delta (ΣΔ) modulator is proposed to be used in low oversampling ratio (OSR) applications. It utilizes a noise-shaped two-step (NSTS) analog-to-digital converter (ADC) in the second stage and benefits its inter-stage gain to provide an extra attenuation of the quantization noise such that the same specifications of a traditional modulator are achieved but with a lower order of noise-shaping. Furthermore, large number of bits is resolved in the second stage while equal number of comparators is used. Compared to the single-loop NSTS ADC, in the proposed structure, the complexity problem of the feedback path and coefficient spreading are eliminated. As an example, a MASH 2-1 sigma-delta modulator has been designed and simulated in a 90 nm CMOS process using Spectre. The achieved resolution is 13.44 effective number of bits in 6.25 MHz signal bandwidth while consuming 19.6 mW power from a single 1 V supply. The sampling frequency is 100 MHz and the simulated figure of merit is 141 fJ/conv-step which shows the efficiency of the proposed modulator.     

Accounting for variability in the design of circuits with organic thin-film transistors

We experimentally verify that the methodology to account for local parameter variations and transistor mismatch known in Si CMOS technologies can be transposed to organic thin-film transistor technologies, and we present a design case that makes use of design for variability. Transistor parameter variation decreases with the square root of the transistor footprint. As a consequence, Monte Carlo simulations which take this effect into account can be executed to better predict the final circuit yield. The design case in this work is an 8-bit, organic RFID transponder chip. The yield prediction by simulations corresponds to the finally observed circuit yield.     

联合多分组接收和模糊逻辑控制功率策略

针对无线网络节约能耗的要求,提出了一种联合多分组接收和模糊逻辑控制功率策略,采用串行干扰消除法,根据无线节点的传输功率等级,将功率等级划分为多分组接收能够正常解码的功率等级,并以任一无线节点到邻接节点的距离、邻接节点的个数和无线节点的剩余能耗为模糊逻辑控制的输入参数来控制各无线节点的功率选择。仿真结果表明,与现有的几种经典的基于功率控制的串行干扰消除算法方案相比,联合多分组接收和模糊逻辑控制功率策略的无线网络具有更大的有效吞吐量及更长的生存时间。     

基于高非线性Sagnac干涉仪的超高速全光NOT门可级联性研究

在未来的通信领域中,全光逻辑门是全光计算机和全光网络的基本单元。目前已经提出了很多实现全光逻辑门的结构和方法,但是全光逻辑的技术瓶颈也出现了,就是怎样能够将单个的全光逻辑门级联起来实现更复杂的逻辑关系。现存的全光逻辑门结构一般不具有很好的可以实现多级连接的级联性,而且现有的对于级联性的分析大都停留在理论层面,而没有与实际情况相结合,所以对于实际应用来说意义很小。提出了一种新型的基于高非线性Sagnac 干涉仪的超高速全光NOT 门,建立了它的数学模型,采用了与实际情况更加接近的高斯脉冲模拟输入光,并且在仿真结果的基础上分析了系统的级联性,对级联性的分析考虑了光纤损耗和走离效应的影响。得到的基本结论表明,所提出的全光逻辑门的结构能够在实际情况下保持良好的级联性。     

全光加密 A?B 逻辑门的实验研究

针对光传输系统单波长信号全光加密的应用需求,基于流密码体制开展了光传输系统物理层全光加密技术的理论分析,设计了基于 SOA-XGM(半导体光放大器-交叉增益调制)的全光 A?B 逻辑门的实验方案,并在实验室搭建了实验系统。实现了速率为10 Gbit/s 的 A?B 逻辑处理,分析了探测光信号功率、泵浦光信号功率和 SOA 注入电流等主要参数对逻辑门输出信号质量的影响,实现了明文光信号的全光加密。     

A new wideband regulated cascode amplifier with improved performance and its application

This paper presents a new high frequency Regulated Cascode (RGC) amplifier with improved performance. The split-length compensation technique is used to increase both the bandwidth and output impedance, and decrease the input impedance of the conventional RGC. The bandwidth of the proposed RGC amplifier is 5.81 GHz, which is about 2.7 GHz larger than that of simple one. The improved performance of the introduced circuit is achieved with no additional passive element and DC power dissipation. In the paper, output impedance and bandwidth of the proposed circuit are derived by using small signal analysis and have also been compared with the traditional one. In addition, a wideband high performance current mirror is designed in the work as an application of the proposed RGC structure. The bandwidth extension ratio (BWER) of the modified wideband current mirror is 1.37. The proposed circuits are designed by using TSMC 0.18 µm CMOS process and BSIM3 Level 49 device model. The circuits are simulated on Spectre simulator of Cadence to validate the analytical results obtained in the paper.     

提升LED驱动芯片视觉刷新率的逻辑电路设计

为了提升LED显示屏的画面质量,设计了能提高LED显示屏视觉刷新率的逻辑电路。该电路将一个显示周期分为32段,每一段包含有128个灰度时钟周期,占空比由12位灰度数据控制。逻辑电路产生的PWM和传统的PWM相比能提高视觉刷新率,最高能将视觉刷新率提高至32倍;能弥补S-PWM( Scrambled-PWM)在灰度数据低时视觉刷新率低的不足。在Cadence软件下进行设计仿真,并在开发板上进行了验证设计的可行性。     

Ag+与Hg2+对G-四链体DNA结构的破坏及其对构筑DNA逻辑门的应用

本工作利用圆二色光谱研究了Ag+与Hg2+对4种代表性G-四链体DNA结构的破坏作用。结果表明Ag+可能通过与碱基G螯合从而破坏G-四链体结构;Hg2+能通过形成T-Hg2+-T碱基对,及其他方式破坏G-四链体结构。含巯基(-SH)的半胱氨酸与Ag+与Hg2+可以发生较强的配位作用,从而使被Ag+与Hg2+破坏后的G-四链体DNA结构得以回复。基于此,一个新颖的Ag+/Hg2+-半胱氨酸-DNA逻辑门得以构筑。     

Biocomputing Based on DNA Strand Displacement Reactions

The high sequence specificity and precise base complementary pairing principle of DNA provides a rich orthogonal molecular library for molecular programming, making it one of the most promising materials for developing bio-compatible intelligence. In recent years, DNA has been extensively studied and applied in the field of biological computing. Among them, the toehold-mediated strand displacement reaction (SDR) with properties including enzyme free, flexible design and precise control, have been extensively used to construct biological computing circuits. This review provides a systemic overview of SDR design principles and the applications. Strategies for designing DNA-only, enzymes-assisted, other molecules-involved and external stimuli-controlled SDRs are described. The recently realized computing functions and the application of DNA computing in other fields are introduced. Finally, the advantages and challenges of SDR-based computing are discussed.