一种通过激光修调产生精确时钟的方法

文章介绍了一种通过修调,可在片内得到精确时钟的方法。该方法由于内部集成了检测电路,只需通过判断pad的输出结果即可得到修调状态,因此可应用于大规模工业化生产。在文章中给出了修调值的选取方法,同时还讨论了影响修调精度的因素。     

Analog signal generator for BIST of wideband IF signals bandpass sigma-delta modulator

This paper presents improvements in generation of wideband and high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma-delta modulator chip. Via increasing the order of the one-bit bandpass sigma-delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma-delta modulator chip's production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.     

一种VLSI零偏差时钟线网布线算法

本文给出了一种时钟线网布线的新算法。算法基本上消化了时钟偏差，并使线网总线长得到了最小化。其关键在于：１在旋转定位的基础上，采用平衡合并的原则构造时钟树拓扑结构，并在合并过程中，保证点与弧之间的连续优化。２根据拓扑表，确定详细布线时的连线走向，从而对总线长作出了进一步的优化。实验结果表明，我们的算法是有效的，能够较好地用一大规模集成电路的时钟线网的布线。     

一种有效的VLSI平面时钟布线算法

本文提出了一种有效的VLSI平面时钟布线算法，通过自顶向下的对时钟汇点交替的进行水平和垂直划分，然后自底向上的沿着切割线方向对两棵子树进行合并来构造一棵平面时钟树，在构造时钟树的同时完成线网的连接。最后采用启发式的障碍避免算法使线网绕开障碍物。     

基于Hough变换的图像档案的表格提取与倾斜校正

本文提出了一种基于Hough变换的图像档案的表格提取与倾斜校正方法。在检测表格线的同时，完成对其端点坐标的同步记录，对于表格图像倾斜角度较小的情况，采用基于线性搬移技术的校正达到图像快速倾斜校正的目的。     

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS

This paper presents a clock generator circuit for a high-speed analog-to-digital converter (ADC). A time-interleaved ADC requires accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at a speed of 166 MS/s, which corresponds to an equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 μm SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies a 0.6 mm² silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted using 1 ps precision.     

支持JTAG协议的芯片测试时钟的解决方案

控制系统时钟激励信号的正确打是芯片内测试的关键所在,以JTAG协议为基础,文章介绍了芯片时钟端口的设计方法以及对芯片进行内测试时外部时钟信号的控制方法,最后,文章提出了一种应用多相时钟芯片的测试规则,满足测试对时序的要求。     

高速多级时钟网布线

提出了一种新的加载缓冲器的时钟布线算法 .该算法根据时钟汇点的分布情况 ,在时钟布线之前对缓冲器进行预先布局 ,并将时钟树的拓扑生成及实体嵌入和层次式的缓冲器布局方法有机结合起来 ,使布线情况充分反映缓冲器对时钟网结构的影响 .实验证明 ,与将缓冲器插入和布局作为后处理步骤相比 ,缓冲器预先插入和布局在很大程度上避免了布线的盲目性 ,并能更加有效地实现各时钟子树的延迟和负载的平衡 .     

A Sufficient Condition for a Smash Product as a Transfinite Left Free Normalizing Extension and Its Application

In this paper, a sufficient condition is given under which the smash product A#H is a transfinite left free normalizing extension of an algebra A. Moreover, the result is applied to a skew semigroup ring, a skew group ring and the quantum group U _q (sl(2)) such that some properties are shown. Received April 14, 1997, Accepted August 10, 1998