Peterson–Gorenstein–Zierler algorithm for skew RS codes

We design a non-commutative version of the Peterson–Gorenstein–Zierler decoding algorithm for a class of codes that we call skew RS codes. These codes are left ideals of a quotient of a skew polynomial ring, which endow them of a sort of non-commutative cyclic structure. Since we work over an arbitrary field, our techniques may be applied both to linear block codes and convolutional codes. In particular, our decoding algorithm applies for block codes beyond the classical cyclic case.     

华为SDH设备时钟ID在网络中的作用分析

通过分析各种网络结构下时钟ID所能起的作用．从而确认时钟ID在简单网络情况下可以避免定时自环．但在复杂网络条件下其作用基本丧失，仍需采取网络规划方法避免定时自环。     

Design and simulation of sequential circuits in quantum-dot cellular automata: Falling edge-triggered flip-flop and counter study

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology, with extremely small feature size and ultralow power consumption comparing with transistor-based technology. Anteriority, basic level-triggered flip-flop designs based on QCA implementation were examined. In this paper, we utilize the unique QCA characteristics and clock zones to design falling edge-triggered J-K flip-flop that is stable and practical. Simulation with the QCADesigner simulator is performed to verify the functionality of the proposed falling edge-triggered flip-flop. This paper also explores the design of counters. Synchronous counters are designed with several different bit sizes and simulation results demonstrate the validity of them.     

实现折叠共栅共源运放MST的时钟馈通频率补偿方法

该文基于二阶系统最小建立时间(MST)理论和阶跃响应分析,提出了一种新型的时钟馈通频率补偿方法.该方法通过MOS电容引入时钟馈通进行频率补偿,无需对运放结构和参数进行调整.在Cadence ADE仿真环境下运用SMIC 0.35μm 2P3M Polyside Si CMOS模型参数,对折叠共源共栅放大器进行了模拟分析.结果表明,补偿后的运放实现了MST状态,并缩短了建立时间22.7%,提高了其响应速度.在0.5pF～2.5pF负载电容范围内,其建立时间近似线性变化,且对应每一负载电容值均达到MST状态.该方法可望应用于高速有源开关电容网络及其相关领域.     

利用频域时钟抖动分析加快设计验证过程

随着数据速率的提高,时钟抖动分析的需求也在与日俱增。本文探讨参考了时钟的作用和时钟抖动对数据抖动的影响,并讨论在E5052B信号源分析仪（SSA）上运行的Agilent E5001A精确时钟抖动分析应用软件所配备的全新测量技术。     

基于法布里-珀罗滤波器的40 GHz全光时钟提取实验

研究了在基于法布里-珀罗（F-P)滤波器的全光时钟提取实验中法布里-珀罗滤波器的精细度和信号码型对时钟提取的影响.根据理论分析,利用精细度为1012的F-P滤波器进行了时钟提取实验,并利用SOA进一步抑制时钟信号中的幅度抖动噪音,改善了时钟信号的质量.最终提取出低幅度起伏、低时间抖动的40 GHz 时钟信号.     

TMR计算系统中的容错锁相同步时钟电路

以数字锁相技术为基础，研制出用于ＴＭＲ计算系统的容错同步时钟电路。该电路工作稳定、具有完善的容错功能并达到相当高程度的时钟同步水平，在１０￣３０ＭＨｚ频率范围工作时，４个冗余时钟模块之间的最大相位差都小于５ｎｓ，叙述了容错同步时钟电路的工作原理和设计原则，并对引起冗余模块间相位差的各种因素进行了分析。     

一种通过激光修调产生精确时钟的方法

文章介绍了一种通过修调,可在片内得到精确时钟的方法。该方法由于内部集成了检测电路,只需通过判断pad的输出结果即可得到修调状态,因此可应用于大规模工业化生产。在文章中给出了修调值的选取方法,同时还讨论了影响修调精度的因素。     

Analog signal generator for BIST of wideband IF signals bandpass sigma-delta modulator

This paper presents improvements in generation of wideband and high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma-delta modulator chip. Via increasing the order of the one-bit bandpass sigma-delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma-delta modulator chip's production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.     

一种VLSI零偏差时钟线网布线算法

本文给出了一种时钟线网布线的新算法。算法基本上消化了时钟偏差，并使线网总线长得到了最小化。其关键在于：１在旋转定位的基础上，采用平衡合并的原则构造时钟树拓扑结构，并在合并过程中，保证点与弧之间的连续优化。２根据拓扑表，确定详细布线时的连线走向，从而对总线长作出了进一步的优化。实验结果表明，我们的算法是有效的，能够较好地用一大规模集成电路的时钟线网的布线。