Effectiveness of RTS/CTS handshake in IEEE 802.11 based ad hoc networks

IEEE 802.11 MAC mainly relies on two techniques to combat interference: physical carrier sensing and RTS/CTS handshake (also known as “virtual carrier sensing”). Ideally, the RTS/CTS handshake can eliminate most interference. However, the effectiveness of RTS/CTS handshake is based on the assumption that hidden nodes are within transmission range of receivers. In this paper, we prove using analytic models that in ad hoc networks, such an assumption cannot hold due to the fact that power needed for interrupting a packet reception is much lower than that of delivering a packet successfully. Thus, the “virtual carrier sensing” implemented by RTS/CTS handshake cannot prevent all interference as we expect in theory. Physical carrier sensing can complement this in some degree. However, since interference happens at receivers, while physical carrier sensing is detecting transmitters (the same problem causing the hidden terminal situation), physical carrier sensing cannot help much, unless a very large carrier sensing range is adopted, which is limited by the antenna sensitivity. In this paper, we investigate how effective is the RTS/CTS handshake in terms of reducing interference. We show that in some situations, the interference range is much larger than transmission range, where RTS/CTS cannot function well. Two independent solutions are proposed in this paper. One is a simple enhancement to the IEEE 802.11 MAC protocol. The other is to utilize directional antennas. Simulation results verify that the proposed schemes indeed can help IEEE 802.11 resolve most interference caused by large interference range.     

IEEE802.11g研究综述

介绍了无线局域网IEEE802.11g标准,详细讲述了IEEE802.11g标准的概念、产生背景、特点、构件及体系结构、发展前景,并探讨了实现IEEE802.11 gWLAN所需的几项关键技术,同时分析了IEEE802.11g标准的网络性能.     

基于信息技术的CTS信息获取

通过信息技术手段高效获取与利用化学、技术与社会信息资源,是化学教学对CTS信息资源的需求和化学教师自身信息素养的提高共同决定的。     

Performance analysis of RTS/CTS scheme in WLAN with the impact of bit errors

To estimate the system performance of RTS/CTS scheme in an error‐prone WLAN channel, this paper proposes a new three‐dimensional Markov model, which considers the impact of bit error on all kinds of frames, and both station short retry limit and long retry limit. The system performance parameters including saturation throughput, packet drop probability, drop time, and average delay are derived using the new Markov model. By comparing the numerical results with simulation results, the model is proved to be more accurate than previous work. The numerical results show that the channel bit error rate has a significant impact not only on system performance, but also on the sensitivity of other system parameters including network scale, channel data rate, and packet length. Copyright © 2010 John Wiley & Sons, Ltd.     

Si~(4+)掺杂对BaZr(BO_3)_2:Eu荧光粉能量传递的影响

采用高温固相法合成了Si4+掺杂的BaZr(BO3)2:Eu红色发光荧光粉。激发光谱表明,不同Si4+掺杂浓度明显使电荷迁移态(CTS)向高能量的位置移动,且改善了样品的发光强度。分析认为,这是由于Si4+的电负性大于所取代的Zr4+,且Si4+的进入影响了Eu3+的配位数,提高了CTS向发光中心的能量传递几率。依据Judd-Ofelt理论计算的强度参数表明,随着Si4+掺杂浓度的增加,Eu3+所处格位的对称性明显降低,增大了Eu3+的跃迁几率,从而改善了发光强度。计算Eu3+间的能量传递几率发现,在掺杂浓度为5%时,Eu3+间的能量传递几率很小,其对荧光粉的发光影响不大。     

适用于EEPROM的低功耗高效率的高压产生电路

本文提出了一种应用于嵌入式EEPROM的低功耗和高效率的高电产生电路。低功耗的实现是基于电容分压电路和控制时钟的稳压电路技术;高效率是由于采用了零阈值Vth MOSFET和电荷传输开关技术的电荷泵。该高电压电路采用0.35 μm CMOS工艺流片。测试结果表明,高电产生电路的功耗约150.48 μW和电荷泵效率高达83.3％,因此高电产生电路也可广泛用于低功耗Flash中。     

ASIC设计中时钟偏移分析

目前的ASIC设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注,因此如何解决它给电路带来的不利影响成了设计中的重要挑战、文章分析了时钟偏移的产生机理,然后提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,最后还分析了如何利用有用的时钟偏移来改善电路的时序。     

ASIC物理设计中的时钟树综合优化研究

以一款基于HJTC 0.18μm工艺的YAK SOC芯片为例,根据其时钟结构,提出一种能有效减小时钟偏移的方法,该方法通过在门级将时钟根节点分解成若干伪时钟源实现.基于该方法,采用布局布线工具,对YAK SOC芯片进行时钟树综合,得到了较好的效果.给出了一种采用缓冲器和反相器相结合构建时钟树以降低时钟树功耗的方法.通过...     

一种高效时钟树综合实现方法

针对ASIC芯片设计中时钟树综合效率和时序收敛的问题,提出了一种高效的时钟树综合方法,特别适用于现代先进深亚微米工艺中的高集成度、高复杂度的设计中。改进了传统时钟树综合方法,通过采用由下至上逐级分步综合的方法实现。该设计方法在SMIC 0.18μm eflash工艺下的一款电力线载波通信芯片中成功流片验证,结果表明分步综合能够在实现传统设计功能的前提下,在完成时序收敛时有效减少不必要的器件插入,从而减小芯片面积,降低整体功耗,有效改善绕线拥塞度。     

用Encounter实现Mesh-Local-Tree结构的时钟设计流程

提出了一种实用的设计流程,即在Cadencd公司的Encounter环境中去实现对网格 本地树(MLT)时钟结构的综合与分析方法.对一个实际工业设计试验的数据表明:运用Clockmesh CRS的综合方式,MLT的时钟架构相对于单一的树结构能够实现更小的时钟偏差(114ps、 171ps).同时,将这种设计流程运用于其他设计中,以比较MLT和CTS不同的设计流程.结果显示,MLT的时钟架构可以实现更小的时钟偏差,同时还可以降低缓冲器的数量,这样也弥补了单一网格结构的功耗问题.