A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC

A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 #m CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which can perform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within 4-0.28 LSB and 4-0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 roW.     

Increase in the Intracellular Bulk Water Content in the Early Phase of Cell Death of Keratinocytes,Corneoptosis, as Revealed by 65 GHz Near-Field CMOS Dielectric Sensor

While bulk water and hydration water coexist in cells to support the expression of biological macromolecules, how the dynamics of water molecules, which have long been only a minor role in molecular biology research, relate to changes in cellular states such as cell death has hardly been explored so far due to the lack of evaluation techniques. In this study, we developed a high-precision measurement system that can discriminate bulk water content changes of ±0.02% (0.2 mg/cm³) with single-cell-level spatial resolution based on a near-field CMOS dielectric sensor operating at 65 GHz. We applied this system to evaluate the temporal changes in the bulk water content during the cell death process of keratinocytes, called corneoptosis, using isolated SG1 (first layer of stratum granulosum) cells in vitro. A significant irreversible increase in the bulk water content was observed approximately 1 h before membrane disruption during corneoptosis, which starts with cytoplasmic high Ca²⁺ signal. These findings suggest that the calcium flux may have a role in triggering the increase in the bulk water content in SG1 cells. Thus, our near-field CMOS dielectric sensor provides a valuable tool to dissect the involvement of water molecules in the various events that occur in the cell.     

一种具有高电源抑制比的低功耗CMOS带隙基准电压源

文章设计了一种适用于CMOS工艺的带隙基准电压源电路，该电路采用工作在亚阈值区的电路结构，并采用高增益反馈回路，使其具有低功耗、低电压、高电源电压抑制比和较低温度系数等特点。     

硅基光子集成研究进展

报道了国际上关于硅基光子集成的最新研究进展和本课题组在该领域的研究成果,包括对一些光收发模块、III-V族/硅基激光器等集成器件的结构改进和工艺的探索,展示了兼容互补金属氧化物半导体工艺的硅基光子集成在信息技术领域中的巨大前景.可以预见,硅基光子集成已成为硅光子学的主要研究内容,硅光子学及硅基光子集成的发展目标是趋向更高速率、更低功耗及更大集成密度.     

电容型传感器接口电路的研究

设计了一种结构简单、新颖的电容型传感器接口电路.电路中放大器的第一级采用折叠式共源共栅结构,提供了较高的增益;第二级采用共源级结构,提高了输出摆幅;采用CMOS开关构成的开关电容电路提高了电路的精度.基于0.6μm CMOS工艺对电路进行了设计,并对整体接口电路进行了仿真.仿真结果表明,与传统的接口电路相比,该电路具有高增益与高精度的特点,从而更好地实现了对微小电容的检测.     

电容式z轴微机械陀螺的噪声抑制

将z轴微机械陀螺两个模态的机械噪声效应等效为各自在单位噪声力作用下的振动,根据陀螺的工作原理得到两个噪声力作用下陀螺敏感模态的机械输出噪声。建立了包含运放和电路板非理想因素在内的接口电路的噪声模型。结合机械噪声模型和接口电路模型噪声,建立了包括结构参数和电路最小检测电容量在内的陀螺的噪声等效输入角速度模型,为陀螺的设计优化提供了参考。分析了结构参数对陀螺等效输入角速度噪声影响,并采用两个参数不同的电容式z轴微机械陀螺进行了实验。结果表明,通过结构参数的调整,将电容式z轴微机械陀螺的输出噪声从414μV/Hz降低至235μV/Hz。     

10 Gb/ s 0. 18 􀀁m CMOS 激光二极管驱动器芯片

基于0．18μm CMOS工艺设计的10Gb／s激光二极管驱动器电路。核心单元为两级直接耦合的差分放大器，电路中采用了并联峰化技术和放大级直接耦合技术以扩展带宽，降低功耗。模拟结果表明，在1．8V电源电压作用下该电路可工作在10Gb／s速率上，输入单端峰峰值为0．3V的差分信号时，在单端50Ω负载上的输出电压摆幅可达到1．4V，电路功耗约为85mW。     

基于0.18μm CMOS工艺的环形行波振荡器

环形行波振荡器（rotary traveling-wave oscillators, RTWOs）是近年提出的一种基于传输线的新型千兆赫兹时钟生成技术,但研究表明该技术同样适用于压控振荡器设计。与普通LC振荡电路不同,环形行波振荡器可以很方便地产生幅度一致的差分多相（360o）振荡信号。本文基于SMIC 0.18μm CMOS工艺设计实现了一个工作于5.8GHz频段的环形行波振荡器,文中同时给出了仿真结果和测试结果。芯片大小为1.5×1.5 mm2。测试结果表明环形行波振荡器实际振荡频率为5.285GHz,相应输出功率6.68dBm,距离载波1MHz处相位噪声为-102dBc/Hz。     

适于视频应用的高数据传输率集成CMOS收发机

这篇文章给出了一个5GHz CMOS射频收发机的设计方案。此设计采用0.18微米射频CMOS加工工艺,集合了最新IEEE802.11n的特性例如多输入多输出技术的专利协议以及其他无线技术,可提供应用在家庭环境中的实时高清电视数据的无线高速传输。设计频率涵盖了从4.9GHz到5.9GHz的ISM频带,每个射频信道的频宽为20MHz。收发机采用了直接上变频发射器和低中频接收器的结构。在没有片上校准的情况下,设计采用双正交直接上变频混频器,得到了超过35dB的镜像抑制。测试结果得到6dB接收机噪声系数以及在-3dBm输出功率时得到发射机EVM结果优于33dB。     

薄膜全耗尽SOICMOS器件和电路

对全耗尽 SOI(FD SOI) CMOS器件和电路进行了研究 ,硅膜厚度为 70 nm.器件采用双多晶硅栅结构 ,即NMOS器件采用 P+多晶硅栅 ,PMOS器件采用 N+多晶硅栅 ,在轻沟道掺杂条件下 ,得到器件的阈值电压接近0 .7V.为了减小源漏电阻以及防止在沟道边缘出现空洞 (V oids) ,采用了注 Ge硅化物工艺 ,源漏方块电阻约为5 .2Ω /□ .经过工艺流片 ,获得了性能良好的器件和电路 .其中当工作电压为 5 V时 ,0 .8μm 10 1级环振单级延迟为 45 ps