Substrate noise isolation improvement in a single-well standard CMOS process

This work describes a fully CMOS compatible methodology, which makes available a pseudo deep n-well in single-well standard CMOS process. The proposed method is based on mask manipulation to accommodate the field implant p-type region into the n-well, and does not require any additional masks or modification in the CMOS process flow. According to the experimental results, the floating NMOS made available by the methodology shows a reduction in the threshold voltage, which implies a slight improvement in its performance, when compared with its standard NMOS counterpart. It was also experimentally demonstrated up to 3 GHz, that the guard-ring field implant/pseudo deep n-well proposed structure improves substrate noise isolation when compared to the classical p+ guard-ring, with a maximum improvement above 20 dB for low frequencies and a minimum of 4 dB at 3 GHz.     

A wireless multi-channel implantable neural recording microsystem based on optimized analog TDM-FDM combination

Crosstalk noise (CT) is a limiting factor to increase the number of channels in analog Time-Division-Multiplexing (TDM)-based Wireless Neural Recording microsystems (WNRs). This paper proposes a novel approach to mitigate and decrease the effect of the CT by combining TDM with Frequency-Division-Multiplexing (FDM). In particular, we evaluate some possible configurations of the TDM-FDM combination and present a system that has less CT than other configurations. A 12-channel WNR based on the proposed system is designed in both system and circuit-level. In this system, channels are first divided into three 4-channel groups and after multiplexing in time domain, they are combined together with FDM method. While the group containing the marker pulse is located in the base-band, the second and third group are shifted to the frequency domain by employing quadrature modulation. The circuit-level of the system is designed and simulated by using 0.18 μm CMOS technology. The designed circuit consumes a power of 1.4 mW at a supply voltage of 1.8 V. The performance of the proposed system is also compared with simple TDM-based WNR. Simulations shows that in the proposed system the CT is considerably decreased.     

Detecting itinerant single microwave photons

Single-photon detectors are fundamental tools of investigation in quantum optics and play a central role in measurement theory and quantum informatics. Photodetectors based on different technologies exist at optical frequencies and much effort is currently being spent on pushing their efficiencies to meet the demands coming from the quantum computing and quantum communication proposals. In the microwave regime, however, a single-photon detector has remained elusive, although several theoretical proposals have been put forth. In this article, we review these recent proposals, especially focusing on non-destructive detectors of propagating microwave photons. These detection schemes using superconducting artificial atoms can reach detection efficiencies of 90% with the existing technologies and are ripe for experimental investigations.     

MASH ΣΔ modulators with a noise-shaped two-step ADC in the second stage

In this paper, a multi-stage noise-shaping (MASH) sigma-delta (ΣΔ) modulator is proposed to be used in low oversampling ratio (OSR) applications. It utilizes a noise-shaped two-step (NSTS) analog-to-digital converter (ADC) in the second stage and benefits its inter-stage gain to provide an extra attenuation of the quantization noise such that the same specifications of a traditional modulator are achieved but with a lower order of noise-shaping. Furthermore, large number of bits is resolved in the second stage while equal number of comparators is used. Compared to the single-loop NSTS ADC, in the proposed structure, the complexity problem of the feedback path and coefficient spreading are eliminated. As an example, a MASH 2-1 sigma-delta modulator has been designed and simulated in a 90 nm CMOS process using Spectre. The achieved resolution is 13.44 effective number of bits in 6.25 MHz signal bandwidth while consuming 19.6 mW power from a single 1 V supply. The sampling frequency is 100 MHz and the simulated figure of merit is 141 fJ/conv-step which shows the efficiency of the proposed modulator.     

Accounting for variability in the design of circuits with organic thin-film transistors

We experimentally verify that the methodology to account for local parameter variations and transistor mismatch known in Si CMOS technologies can be transposed to organic thin-film transistor technologies, and we present a design case that makes use of design for variability. Transistor parameter variation decreases with the square root of the transistor footprint. As a consequence, Monte Carlo simulations which take this effect into account can be executed to better predict the final circuit yield. The design case in this work is an 8-bit, organic RFID transponder chip. The yield prediction by simulations corresponds to the finally observed circuit yield.     

Memristor emulator with tunable characteristic and its experimental results

In this study, operational transconductance amplifier (OTA) based simple and practical TiO₂ memristor emulator is presented. The proposed memristor emulator employs a multi-outputs OTA, an analog multiplier and a resistor and a capacitor. The parameters of the proposed memristor emulator can be tuned electronically by changing the biasing current of the OTA. Change of the transconductance gain of the OTA provides an advantage: “externally controllable memristor”. Non-volatile resistive switching characteristics and an application of this proposed memristor are given. Also, the memristor emulator is implemented using the commonly available OPA860. The effectiveness of the proposed memristor emulator is verified by the experimental results, which show good agreement with the theoretical and simulation results.     

一种用于电流型电化学传感器的CMOS模拟前端芯片

本文提出了一种用于电流型电化学传感器的CMOS模拟前端芯片,芯片具有高度可编程性,其内部集成了可通过I2C接口总线与外部控制芯片通信的可配置数字模块电路。结合incremental型sigma-delta模数转换器与数字域相关双采样技术,提出并实现了一种新的两次采样的系统架构。该芯片基于华虹宏力0.18μm标准CMOS工艺流片,消耗芯片面积为1.3 mm × 1.9 mm,测试结果表明：该芯片16位数字输出具有高精度,高线性度特性,可检测溶液中磷酸根离子浓度的精度为0.01 mg/L。     

MCML结构高速数模转换器的设计

本文基于MCML结构,采用TSMC 0．18μm 1P6M CMOS标准工艺设计方法,通过模拟仿真试验,设计出了一个8位分段式全温度计编码的高速数模转换器,该电路在采样频率为1 GHZ,输入正弦波频率为122 MHz时,SFDR达到了58．35 dB,在采样频率为2 GHZ,输入正弦波频率为244 MHz时,SFDR达到了50．21 dB。     

基于片上变压器耦合的CMOS功率放大器设计

设计了一个2 GHz全集成的CMOS功率放大器(PA),该PA的匹配网络采用片上变压器实现,片上变压器用来实现单端信号和差分信号之间的转换和输入、输出端的阻抗匹配。采用ADS Momentum软件对片上变压器进行电磁仿真,在2 GHz频点,输入、级间和输出变压器的功率传输效率分别为74.2%,75.5%和78.4%。该PA基于TSMC 65 nm CMOS模型设计,采用Agilent ADS软件进行电路仿真,仿真结果表明:在2.5 V供电电压、2 GHz工作频率点,PA的输入、输出完全匹配到50Ω(S11=–22.4 d B、S22=–13.5 d B),功率增益为33.2 d B,最高输出功率达到23.4 d Bm,最高功率附加效率(PAE)达到35.3%,芯片面积仅为1.01 mm2。     

应用于CMOS图像传感器的联合降噪插值算法研究

提出了一种可应用于CMOS图像传感器的联合并行图像预处理算法,其中,色彩插值算法采用双线性插值法和边缘导向插值法相结合的方式来完成色彩还原,而降噪算法采用带阈值的空间自适应滤波降噪算法,在硬件语言描述算法时,将两种算法的处理过程进行了联合处理.实验仿真结果表明,通过对算法进行ISE仿真和Matlab显示处理,得到色彩饱和度较高的彩色图像,峰值信噪比(PSNR)为30～36 dB.整个处理过程有效地简化了片上系统(SOC)的图像处理过程,提高了算法的运算速度,节省了芯片面积且降低了系统功耗,为CMOS图像传感器的片上系统集成化设计提供了技术支持.