Energy minimization and design for testability

The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables.     

群时延精确设计的全差分四阶Bessel滤波器

采用MOS管有源电阻,提出了一种全差分R-MOSFET-C四阶Bessel有源低通滤波器,.通过调节工作于亚阈值区的CMOS管的沟道导纳补偿电阻值的大小,能抵消集成电路制造工艺中电阻值的一致偏差,实现Bessel有源滤波器群时延的精确设计.根据无源滤波器的状态方程完成有源滤波器的综合,应用3.3V,0.5μm CMOS工艺完成了群时延大小为0.75μs的四阶Bessel低通滤波器的管极计算机仿真,仿真结果表明所提电路正确有效,适于全集成.     

大规模集成电路浮栅ROM器件总剂量辐射效应

提出了一种大规模集成电路总剂量效应测试方法:在监测器件和电路功能参数的同时,监测器件功耗电流的变化情况,分析数据错误和器件功耗电流与辐射总剂量的关系.根据该方法利用60Co γ射线进行了浮栅ROM集成电路(AT29C256)总剂量辐照实验,研究了功耗电流和出错数量在不同γ射线剂量率辐照下的总剂量效应,以及参数失效与功能失效时间随辐射剂量率的变化关系,并利用外推实验技术预估了电路在空间低剂量率环境下的失效时间.     

2.5Gb/s和3.125Gb/s速率级0.35μmCMOS限幅放大器

采用了TSMC0.35μm CMOS工艺实现了可用于SONET/SDH2.5Gb/s和3.125Gb/s速率级光纤通信系统的限幅放大器。通过在芯片测试其最小输入动态范围可达8mVp—p，单端输出摆幅为400mVp-p，功耗250mW，含信号丢失检测功能，可以满足商用化光纤通信系统的使用标准。     

基于MOBILE的JK触发器设计

介绍了一种新型量子逻辑单元电路——单稳双稳转换逻辑单元及其工作原理,在此基础上探讨并设计了以MOBILE为基本单元电路的具有同步置位复位功能的边沿型JK触发器电路,从而丰富了量子电路中触发器的类型     

10 Gb/ s 0. 18 􀀁m CMOS 激光二极管驱动器芯片

基于0．18μm CMOS工艺设计的10Gb／s激光二极管驱动器电路。核心单元为两级直接耦合的差分放大器，电路中采用了并联峰化技术和放大级直接耦合技术以扩展带宽，降低功耗。模拟结果表明，在1．8V电源电压作用下该电路可工作在10Gb／s速率上，输入单端峰峰值为0．3V的差分信号时，在单端50Ω负载上的输出电压摆幅可达到1．4V，电路功耗约为85mW。     

128×128红外焦平面阵列时序分析与温控电路设计

介绍了微测辐射热计的 12 8× 12 8凝视型非致冷红外热像仪的系统框图 ,论述了一种新型的红外焦平面阵列温控电路设计方案以及读出电路时序的FPGA实现方法 .该方案具有高集成度、高精度、低成本、布线简单等优点 ,为热像仪系统的研制开发提供了设计思想 .     

Modular implementation of efficient self-checking checkers for the Berger code

A technique for designing efficient checkers for conventional Berger code is proposed in this paper. The check bits are derived by partitioning the information bits into two blocks, and then using an addition array to sum the number of 1's in each block. The check bit generator circuit uses a specially designed 4-input 1's counter. Two other types of 1's counters having 2 and 3 inputs are also used to realize checkers for variable length information bits. Several variations of 2-bit adder circuits are used to add the number of 1's. The check bit generator circuit uses gates with fan-in of less than or equal to 4 to simplify implementation in CMOS. The technique achieves significant improvement in gate count as well as speed over existing approaches.     

Thermal Monitoring of Self-Checking Systems

With the increasing power density in integrated systems resulting from scaling down, the occurrence of field failures due to overheating has considerably increased. Faulty operation can be prevented by on-line temperature monitoring. This paper deals with questions of on-line temperature monitoring in safety-critical systems. First the possible temperature sensors are reviewed and basic principles of self-checking systems including such sensors are detailed, then a new temperature sensor cell with extremely good parameters designed especially for DfTT applications is presented. The basic questions of integrating thermal sensors into self-checking systems are also discussed.     

Shorts in self-checking circuits

It has been noted by several authors that the classical stuck-at logical fault model might not be an appropriate representation of certain real failures occurring in integrated circuits. Shorts are an important class of such faults. This article gives a detailed analysis of the effects of shorts in self-checking circuits and proposes techniques for dealing with them. More precisely, we show that, unlike other faults such as stuck-at, stuck-on, and stuck-open—which produce only single errors in the place they occur—shorts can produce double errors on the two shorted lines. In particular, feedback shorts can produce double errors on the two shorted lines. The double error is unidirectional for some feedback shorts and non-unidirectional for some others. Furthermore, in some technologies (e.g., CMOS), non-feedback shorts can also produce double non-unidirectional errors. We also show that unlike stuck-at, stuck-on, and stuck-open faults, redundant shorts can destroy the SFS property. Then we propose several techniques for coping with these problems and we illustrate the results by circuit implementation examples.The present study is given for NMOS and CMOS circuits but we show that it is valid for any other technology.