开关布局中本质不同的开关线路计算

通过对开关布局问题的研究，来解决一类象开关线路一样比较特殊，比较复杂的布局优化问题。从而寻找出这类问题的全局优化算法。本应用对称群对集合的作用，轨道，不动点等讨论了开关布局问题，给出了本质不同的开关线路个数的计算公式。     

Layout-Specific Circuit Evaluation in 3-D Integrated Circuits

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit evaluation, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D.     

Lowpass and bandpass transadmittance filter using operational amplifier pole

A new topology simultaneously implementing lowpass (LP) and bandpass (BP) transadmittance filtering signals using a single operational amplifier (OA), one capacitor, and two resistors is presented. The input impedance is very high which is essential for cascading without employment of buffers. The circuit uses absolute minimum number of active and passive components. The filter employs pole-model of OA and as such has acquired suitability for extended frequency operation. The circuit permits separate adjustment of natural frequency (ω₀) and quality factor (Q) in an orthogonal manner. The circuit has low sensitivity figures unlike the reported single amplifier biquads. The PSPICE simulation results are included.     

On the Realization of Current－Mode Continuous－Time Operational Transconductance Capacitance Filter

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全耗尽CMOS／SOI技术的研究进展

ＳＯＩ材料技术的成熟，为功耗低，抗干扰能力强，集成度高，速度快的ＣＭＯＳ／ＳＯＩ器件的研制提供了条件，分析比较了ＣＭＯＳ／ＳＯＩ器件与体硅器件的差异，介绍了国外薄膜全耗尽ＳＯＩ技术的发展和北京大学微电子所的研究成果。     

Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity

To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown.     

Low-Power Adaptive Biased Integrated Amplifiers

In this paper the author will present the working principle and the applications of a novel adaptive biasing topology, designed to decrease the stand-by power dissipation without affecting the transient performance of low-power amplifiers. The proposed circuit, whose principle and circuit topology can be implemented both in CMOS and in bipolar standard technologies, gives a biasing current whose value depends on the applied input differential voltage and can be set according to the requested transient performance constraints. The adaptive architecture can be utilized in the design of high-efficient low-power operational amplifiers, for the biasing of both the input stage (where the input source current is dynamically increased) and the output stage (where the output current can be controlled and limited). These amplifiers show a very good behaviour, evaluated in terms of two efficiency factors, if compared with those of other adaptive solutions and class-AB topologies, proposed in the literature. Simulation results and also measurements on a chip prototype, fabricated in a standard CMOS technology, are finally presented.     

Laser nanosources based on planar photonic crystals as new platforms for nanophotonic devices

Two-dimensional photonic crystal lasers have been fabricated on III–V semiconductor slabs. Tuning of the spontaneous emission in micro and nanocavities has been achieved by accurate control of the slab thickness. Different structures, some of them of new application to photonic crystal lasers, have been fabricated like the Suzuki-phase or the coupled-cavity ring-like resonators. Laser emission has been obtained by pulsed optical pumping. Optical characterization of the lasing modes have been performed showing one or more laser peaks centred around 1.55 μm. Far field characterization of the emission pattern has been realized showing different patterns depending on the geometrical shape of the structures. These kinds of devices may be used as efficient nanolaser sources for optical communications or optical sensors.     

Broadband Analysis of Holographic Power Combining Circuits

Holography is a promising technique for power combining applications in the frequency range of short millimeter and submillimeter waves. In this paper, quasi-optical holographic power combining circuits are investigated. An equivalent network is utilized which rigorously models horn arrays and biperiodic dielectric structures in order to design computer-generated holograms. We apply the network model to a 5-element quasi-optical power combiner and demonstrate its capability. The hologram is designed for 150 GHz and has an efficiency of 92.5 % with a 90 % bandwidth of 5.3 %. With the aid of a broadband waveguide power divider and a vector field measurement system, the circuit is analyzed.     

超大规模集成电路中互连结构的逻辑模型

本文首次提出一种新观点，超大规模集成电路中互连结构的等效模型应具有层次性，对于底层的电路设计，应将互加看作一种具有分布参数的多端口网络，而对于高层次的模块设计，则应将互连看作一种逻辑元件，基于这种观点，本文提出了一种表格型的逻辑模型，它可以将互连产生的三种主要负效应：串扰、延迟和信号变形人武部考虑在内。