重影消除自适应均衡芯片设计

提出了一种重影消除自适应均衡芯片设计．该芯片采用自适应算法、内置576抽头数字滤波器，可完成重影消除的所有功能。芯片高度集成，内嵌DSP控制器、存储器、同步检测器、D／A、A／D及用户编程。该芯片采用3．3V电源电压、0．35μm CMOS工艺生产制造，80-pin的QFP封装；在典型工作频率下最大功耗为1．3W。     

一种应用于WiMAX协议的全集成3.5GHzCMOS功率驱动放大器

A fully integrated CMOS differential power amplifier driver(PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements,a transmission line transformer is used as the output matching network.A differential inductance constitutes an inter-stage matching network.Meanwhile,an on chip balun realizes input matching as well as single-end to differential conversion.The PAD is fabricated in a 0.13μm RFCMOS process.The chip size is 1.1×1.1 mm~2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.     

CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm~2.     

无线射频识别系统中的可能攻击

文章分析了无线射频识别系统中的可能攻击,包括针对标签和阅读器的攻击和针对后端数据库的攻击。     

基于Multisim 10的射频LNA仿真和设计

NI Multisim 10是著名的EDA软件,其仿真功能非常强大,RF电路中LNA的设计是一个难题。使用Multisim设计RF LNA电路,利用虚拟网络分析仪和Smith圆图,对典型RF LNA电路的各种参数进行仿真测试,进而设计阻抗匹配网络,优化电路性能,在设计实践中取得了很好的效果。这对于通信电子产品的设计,对于RF电路的教学和创新型实验具有重要的意义。     

A low power and low phase-noise 91~96 GHz VCO in 90 nm CMOS

This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (C_in) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91~96 GHz, close to the simulated (92.1~96.7 GHz) and the calculated one (92.2~98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of – 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of ?188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm², i.e. 0.315 mm².     

900MHz CMOS锁相环/频率综合器

采用TSMC 0 .2 5μm CMOS技术设计实现了高速低功耗光纤通信用限幅放大器.该放大器采用有源电感负载技术和放大器直接耦合技术以提高增益,拓展带宽,降低功耗并保持了良好的噪声性能.电路采用3.3V单电源供电,电路增益可达5 0 d B,输入动态范围小于5 m Vpp,最高工作速率可达7Gb/ s,均方根抖动小于0 .0 3UI.此外核心电路功耗小于4 0 m W,芯片面积仅为0 .70 mm×0 .70 m m.可满足2 .5 ,3.12 5和5 Gb/ s三个速率级的光纤通信系统的要求.     

0．8μm SOI CMOS技术及电路研制

SOI CMOS技术在一些特殊应用领域中有着体硅无法比拟的优势文中叙述采用SIMOX材料和0.8μm SOI CMOS工艺加固技术成功研制出抗辐射性能较好的器件和电路,并且给出了SOI CMOS器件的特性随辐照总剂量的变化关系,试验电路通过了总剂量500 Krad(Si)钴60γ射线辐照实验。     

基于以太网的嵌入式视觉传感器

本文介绍了基于硬件协议栈的以太网和DSP的嵌入式视觉传感器.给出了系统的硬件设计和图像采集传输的软件流程,并以圆尺寸检测为例介绍系统的实现效果.     

Investigation of RF sputtered PSG films for MEMS and semiconductor devices

In this work, we report the preparation of phospho-silicate-glass (PSG) films using RF magnetron sputtering process and its application as a sacrificial layer in surface micromachining technology. For this purpose, a 76 mm diameter target of phosphorus-doped silicon dioxide was prepared by conventional solid-state reaction route using P₂O₅ and SiO₂ powders. The PSG films were deposited in a RF (13.56 MHz) magnetron sputtering system at 200-300 W RF power, 10-20 mTorr pressure and 45 mm target-to-substrate spacing without external substrate heating. To confirm the presence of phosphorus in the deposited films, hot-probe test and sheet resistance measurements were performed on silicon wafers following deposition of PSG film and a drive-in step. As a final confirmatory test, a p-n diode was fabricated in a p-type Si wafer using the deposited film as a source of phosphorus diffusion. The phosphorus concentration in the target and the deposited film were analyzed using energy dispersive X-rays (EDAX) tool. The etch rate of the PSG film in buffered HF was measured to be about 30 times higher as compared to that of thermally grown SiO₂ films. The application of RF sputtered PSG film as sacrificial layer in surface micromachining technology has been explored. To demonstrate the compatibility with MEMS process, micro-cantilevers and micro-bridges of silicon nitride were fabricated using RF sputtered PSG as a sacrificial layer in surface micromachining. It is envisaged that the lower deposition temperature in RF sputtering (<150 °C) compared to CVD process for PSG film preparation is advantageous, particularly for making MEMS on temperature sensitive substrates.