Wideband Low‐Reflection Transmission Lines for Bare Chip on Multilayer PCB

The pad pitch of modern radio frequency integrated circuits is in the order of few tens of micrometers. Connecting a large number of high‐speed I/Os to the outside world with good signal fidelity at low cost is an extremely challenging task. To cope with this requirement, we need reflection‐free transmission lines from an on‐chip pad to on‐board SMA connectors. Such a transmission line is very hard to design due to the difference in on‐chip and on‐board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow‐to‐wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection‐free microstrip. To verify the concept, several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that the impedance variation is less than 3 Ω for a 50 Ω microstrip and S11 better than –9 dB for the frequency range 1 GHz to 6 GHz when the width changes from 165 µm to 940 µm, and substrate thickness changes from 100 µm to 500 µm.     

High-Selectivity Switched-Capacitor Bandpass Filter with Quasi-Continuous Quality Factor Tunability

This paper describes the design and implementation of a second-order switched-capacitor (SC) bandpass (BP) filter with very wide quality factor (Q) programmability range. The filter selectivity is digitally programmed by varying the effective sampling frequency of an SC branch, without modifying any capacitor value. The proposed approach allows a quasi-continuous Q-factor tunability avoiding, in principle, the inherent quantization error associated to any traditional programming technique. Automatic Q-factor tuning is performed by using a scheme based on an amplitude-locking loop approach. Experimental results obtained from a 0.8-m CMOS integrated prototype demonstrate the versatility of the proposed technique for high-Q SC BP filters.     

Alternative Realizations of CMOS Current Feedback Amplifiers for Low Voltage Applications

Two variants of a new current feedback amplifier (CFA) are presented in this paper. These CFAs are realized in CMOS technology and both are capable of working at low voltages. It is shown that one circuit performs better than the other by virtue of an increased impedance at its Z terminal achieved through the use of additional transistors. Analysis of both variants of the current conveyor and buffer that form the current feedback amplifier gives an insight into the location of primary poles and zeros of the CFAs. Simulation results indicate an overall gain bandwidth product in excess of 59 MHz and 102 MHz for each circuit at a gain of –10 and with a 3.3 V supply. Experimental results from a chip fabricated in a 0.35 m CMOS technology agree closely with the simulation results.     

信息MEMS技术

介绍了信息MEMS技术的研究内容和研究进展,分析了信息MEMS技术对光通信和移动通信的影响,提出了我国发展信息MEMS技术的建议。     

RF CMOS body-effect circuits

After a theoretical and analytical study of the body effect in MOS transistors, this paper offers two useful models of this parasitic phenomenon. Thanks to these models, a design methodology, which takes advantage of the bulk terminal, allows to turn this well-known body-effect drawback into an analog advantage, giving thus an efficient alternative to overcome the design constraints of the CMOS VLSI wireless mass market. To illustrate the approach, four RF building blocks are presented. First, a 0.9 V 10 dB gain LNA, covering a frequency range 1.8-2.4 GHz, thanks to a body-effect common mode feedback, is detailed. Secondly, a body-effect linearity controlled pre-power amplifier is presented exhibiting a 5 dB m input compression point (ICP1) variation under 1.8 V power supply for half the current consumption. Lastly, two mixers based on body-effect mixing are presented, which achieve a 10 dB conversion gain under 1.4 V for a −52 dB LO-to-RF isolation. Well suited for low-power/low-voltage applications, these circuits implemented in a 0.18 μm CMOS VLSI technology are dedicated to multi-standard architectures and system-on-chip implementations.     

New CMOS Fully‐Differential Transconductor and Application to a Fully‐Differential Gm‐C Filter

A new CMOS voltage‐controlled fully‐differential transconductor is presented. The basic structure of the proposed transconductor is based on a four‐MOS transistor cell operating in the triode or saturation region. It achieves a high linearity range of ± 1 V at a 1.5 V supply voltage. The proposed transconductor is used to realize a new fully‐differential Gm‐C low‐pass filter with a minimum number of transconductors and grounded capacitors. PSpice simulation results for the transconductor circuit and its filter application indicating the linearity range and verifying the analytical results using 0.35 μm technology are also given.     

A Broadband Quadrature-Modulator in Standard 0.13 μm CMOS

A polyphase filtering topology is proposed which uses parallel switchable RC-networks for accurate broadband 90^∘ phasing. A 0.13μm CMOS prototype using the quadrature-generation network in a direct-conversion quadrature-modulator achieves a measured image-rejection ratio of −39 dBc or better in 0.6–2.5 GHz while consuming only 66 mW from a 2.2 V single supply. Esa Tiiliharjuwas born in Rovaniemi, Finland, in 1966. He received the M.Sc. degree in Information Technology in 1995, and the Lic.Tech degree in electrical engineering in 1998, both from Helsinki University of Technology, Finland. From 1996 to July 1997 he was employed as an assistant at Helsinki University of Technology. He has held a position as a research assistant since 1997, and he is currently working towards his Ph.D. degree in the Electronic Circuit Design Laboratory at Helsinki University of Technology. His research interests include the design of integrated low-power circuits for portable telecommunication applications. He has designed and measured several integrated circuits for this application area. He is the author or co-author of several internationally-refereed conference and journal publications on analog integrated circuits. Kari A.I. Halonenwas born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from the Helsinki University of Technology (HUT) in 1982 and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, Heverlee, Belgium, in 1987. From 1982 to 1984, he was with HUT as an Assistant and with the Technical Research Center of Finland as a Research Assistant. From 1984 to 1987, he was a Research Assistant with the E.S.A.T. Laboratory, Katholieke Universiteit Leuven, with a temporary grant from the Academy of Finland. Since 1988, he has been with the Electronic Circuit Design Laboratory, HUT, as a Senior Assistant from 1988 to 1990, and as the Director of the Integrated Circuit Design Unit of the Microelectronics Center from 1990 to 1993. He was on leave of absence during the academic year 1992–1993, acting as Research and Development Manager with Fincitec Inc., Finland. From 1993 to 1996, he was an Associate Professor, and since 1997, he has been a full Professor with the Faculty of Electrical Engineering and Telecommunications, HUT. He became the Head of Electronic Circuit Design Laboratory year 1998. He was the Technical Program Committee Chairman for the European Solid-State Circuits Conference in 2000. He is the author or coauthor of over 150 international and national conference and journal publications on analog integrated circuits, and holds several patents on analog integrated circuits. His research interests are in CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications. Dr. Halonen was an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–PART I: FUNDAMENTAL THEORY AND APPLICATIONS from 1997 to 1999. He has been a Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He received the BeatriceWinner Award from the IEEE International Solid-State Circuits Conference in 2002.[c-halonen.eps]     

CMOS image sensors for sensor networks

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 μm CMOS process. The imagers embed an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low power operation. This characteristics allow the sensor to operate in different lighting conditions and for years on the sensor network node power budget. Eugenio Culurciello (S’97–M’99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from Johns Hopkins University, Baltimore, MD. In July 2004 he joined the department of Electrical Engineering at Yale University, where he is currently an assistant professor. He founded and instrumented the E-Lab laboratory in 2004. His research interest is in analog and mixed-mode integrated circuits for biomedical applications, sensors and networks, biological sensors, Silicon on Insulator design and bio-inspired systems. Andreas G. Andreou received his Ph.D. in electrical engineering and computer science in 1986 from Johns Hopkins University. Between 1986 and 1989 he held post-doctoral fellow and associate research scientist positions in the Electrical and Computer engineering department while also a member of the professional staff at the Johns Hopkins Applied Physics Laboratory. Andreou became an assistant professor of Electrical and Computer engineering in 1989, associate professor in 1993 and professor in 1996. He is also a professor of Computer Science and of the Whitaker Biomedical Engineering Institute and director of the Institute’s Fabrication and Lithography Facility in Clark Hall. He is the co-founder of the Johns Hopkins University Center for Language and Speech Processing. Between 2001 and 2003 he was the founding director of the ABET accredited undergraduate Computer Engineering program. In 1996 and 1997 he was a visiting professor of the computation and neural systems program at the California Institute of Technology. In 1989 and 1991 he was awarded the R.W. Hart Prize for his work on mixed analog/digital integrated circuits for space applications. He is the recipient of the 1995 and 1997 Myril B. Reed Best Paper Award and the 2000 IEEE Circuits and Systems Society, Darlington Best Paper Award. During the summer of 2001 he was a visiting professor in the department of systems engineering and machine intelligence at Tohoku University. In 2006, Prof. Andreou was elected as an IEEE Fellow and a distinguished lecturer of the IEEE EDS society. Andreou’s research interests include sensors, micropower electronics, heterogeneous microsystems, and information processing in biological systems. He is a co-editor of the IEEE Press book: Low-Voltage/Low-Power Integrated Circuits and Systems, 1998 (translated in Japanese) and the Kluwer Academic Publishers book: Adaptive Resonance Theory Microchips, 1998. He is an associate editor of IEEE Transactions on Circuits and Systems I.     

A low-power RF integrated circuit for implantable sensors

A low-power low-voltage analog signal processing circuit has been designed, fabricated, and tested. The circuit is capable of processing an analog sensor current and producing an ASK modulated digital signal with modulating signal frequency proportional to the sensor current level. An on-chip regulator has been included to stabilize the supply voltage received from an external RF power source. The circuit can operate with a power supply as low as 1 V and consumes only about 20 μW of power, which is therefore very suitable for implantable biomedical applications. The whole chip was laid out and fabricated in a 0.35 μm bulk CMOS technology. Experimental results show good agreement with the simulation results.