LSC87中嵌入式ROM内建自测试实现

LSC87芯片是与Intel8086配套使用的数值协处理器，体系结构复杂，有较大容量的嵌入式ROM存储器，考虑到与Intel8087的兼容性和管脚的限制，必须选择合适的可测性设计来提高芯片的可测性。文章研究了LSC87芯片中嵌入式ROM存储器电路的设计实现，然后提出了芯片中嵌入式ROM电路的内建自测试，着重介绍了内建自测试的设计与实现，并分析了采用内建自测试的误判概率，研究结果表明，文章进行的嵌入式ROM内建自测试仅仅增加了很少的芯片面积开销，获得了满意的故障覆盖率，大大提高了整个芯片的可测性。     

Built-in ESD Protection for RFID Tag ICs

The built-in Electro-Static discharge (ESD) protection circuits for Radio frequency identification (RFID) tag ICs are proposed.The ESD protection function is built into the rectifier and amplitude limiter.The rectifier and limiter are connected directly to the RF interface,and some transistors can discharge the larger current.These transistors can be used to build ESD protection circuits,through the redesign and optimization.The built-in ESD protection circuits can improve the ESD protection level and reduce the layout area.The circuits have been fabricated in 0.18μm CMOS process.The test results show that the built-in ESD protection circuits work well under 4kV ESD pressure and save as much as 72％ of the layout area compare with foundry standard ESD protection cells.     

An embedded 1149.4 extension to support mixed-signal debugging

Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase.The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.     

Constrained parity testing

A generalized testing technique called constrained parity testing is presented for detecting multiple stuck-at faults in any single-output irredundant combinational network by verifying the subparities of the network. Implementation independent testability conditions are established for single- and multiple-input stuck-at faults. A spanning parity signature (SPS) is introduced to detect vacuous faults, which include all the input stuck-at faults and a majority of all other multiple stuck-at faults. The SPS is considered for testing all stuck-at faults in networks with small numbers of fanout lines, and a method of deriving tests for nonvacuous faults is proposed. For networks with large fanouts, a hybrid scheme by combining with syndrome testing is suggested to eliminate or reduce the need for expensive fault simulation. The proposed technique is a theoretical generalization of many existing methods and offers advantages such as versatility, flexibility, low test volume, low test time, high fault coverage, and reduced fault simulation and test generation costs.     

一种提高锁相环抖动测量精度的方法

根据高速、高精度锁相环抖动测量的需要,提出了一种对抖动线性放大的方法。这种方法将ps级的抖动放大为一定脉宽的脉冲信号,然后再通过一些简单的测试电路,对放大后的脉冲信号进行测量。由于对原来的微小抖动进行了线性放大,从而极大地提高了抖动测量的精度。基于0.8μm CMOS工艺,采用MOSFET LEVEL=2模型,对结论进行了SPICE仿真验证。     

A Novel BIST Approach for Testing Input/Output Buffers in SoCs

A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.     

Simulation for capacitance correction from Nyquist plot of complex impedance–voltage characteristics

The impression of series resistance on unipolar semiconductor device’s capacitance–voltage spectrum is discussed by conventional impedance and admittance analysis, and it is shown that series resistance may cause large errors in capacitance–voltage data. It is shown that the existence of such errors can be deduced from suitable complex impedance measurement obtained during the capacitance–voltage measurement process and this information can be used to correct the distorted capacitance values. A theoretical analysis and computer simulation are presented in order to illustrate the nature of the problem and the technique by which accurate depletion region capacitance can be obtained.     

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths

In this paper an effective Built-In Self-Test (BIST) scheme for the shifter-accumulator pair (accumulation performed either by an adder or an ALU) which appears very often in embedded processor, microprocessor or DSP datapaths is introduced. The BIST scheme provides very high fault coverage (>99%) with respect to the stuck-at fault model for any datapath width with a regular, very small and counter-generated deterministic test set, as it is verified by a comprehensive set of experiments.     

Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments

The goal of this work is to analyze the performance of PN junction-based Built-in Current Sensors (BICS) for I _DDQ testing. Two types of BIC Sensors are analyzed: one based on a simple PN junction as the sensing element (DBICS), and the other based on a lateral BJT (PBICS). The sensitivity, speed and performance of the BICS are studied by showing their dependence on circuit parameters. Design constraints of such sensors in order to achieve performance criteria on CUT and BICS are analyzed. The dynamic analysis of the BICS is compared with experimental results when the PN junction BICS are used on a CMOS circuit.     

内置式网管技术

阐述了“以网管网”的“TMN网管”向“内置式网管”进化的走势,说明了“TINA网管”正是融入通信网内部的“内置式网管”,因而在结构上不再需要分立的TMN.