Test generation,design-for-testability and built-in self-test for arithmetic units based on graph labeling

In this article we discuss a test generation, design-for-testability and built-in self-test methodology for two-dimensional iterative logic arrays (ILAs) that perform arithmetic functions. Our approach is unique because a single graph labeling procedure is used to generate test vectors, implement design-for-testability as well as design the circuitry for built-in self-test. The graph labeling is based on mathematical properties of full-addition such as symmetry and self-duality. Circuit modifications are introduced by a systematic procedure based on the graph labeling, that enable them to be tested with a fixed number of tests irrespective of their size. The approach is novel as it also greatly simplifies the processes of on-chip test vector generation and response comparison that are necessary for built-in self-test. Each circuit module is tested in a pseudo-exhaustive manner with deterministic as opposed to random test sequences. This results in a comprehensive test of the circuit for which built-in self-test is designed.This research was supported by the General Electric Company and by the Semiconductor Research Corporation under contracts SRC RSCH 88-DP-108 at the University of Illinois and SRC RSCH 89-DP-142 at the University of Texas at Austin.     

基于变周期重播种LFSR的测试生成

基于重播种的LFSR结构的伪随机测试生成中包含的冗余测试序列较多,因而其测试序列长度仍较长,耗费测试时间长,测试效率不高。针对此状况,提出基于变周期重播种的LFSR结构的测试生成方法。该方法可以有效地跳过伪随机测试生成中的大量冗余测试序列。在保证电路测试故障覆盖率不变的条件下,缩短总测试序列的长度。分析结果表明,同定长重播种方法相比,该方法能以较少的硬件开销实现测试序列的精简,加快了测试的速度,提高了电路测试诊断的效率。     

An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR

Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.     

ZnO纳米粒子自建场的形成及对其光电特性的影响

The effect of built-in field on the surface photovoltage(SPV) response of ZnO nanoparticles was investigated by means of surface photovoltage spectroscopy(SPS). From the results of in situ SPS in atmosphere and in vacuum, we suggest that the built-in field should be a main condition for producing SPV response. By comparison of SPS with PL in vacuum as well as in atmosphere, we deduce that by changing the ambience of ZnO, its functional properties can be modulated.     

Investigation of Cu2ZnSnS4 thin-film solar cells with carrier concentration gradient

To investigate the effect of carrier concentration gradient on Cu₂ZnSnS₄ (CZTS) thin-film solar cells, the properties of CZTS solar cells were studied by numerical method. The photovoltaic performances of carrier concentration gradient CZTS solar cells were calculated by the solutions of Poisson's equation, continuity equation, and current density equation using AFors-Het v2.4 program. The carrier concentration gradient was changed to analyze its effect. Compared with CZTS solar cells without carrier concentration gradient, the photovoltaic performances of CZTS solar cells can be enhanced by using carrier concentration gradient absorber. The carrier concentration gradient can extend the distribution region of built-in electric field, which is beneficial to the drift of photo-generated carriers. However, the carrier concentration gradient also affects the recombination and series resistances of solar cells. When the defect density of CZTS layer is high, the photo-generated carriers are affected significantly by recombination, resulting in slight effect of carrier concentration gradient. Therefore, the defect density should be reduced to enhance the effect of carrier concentration gradient on improving conversion efficiency of CZTS thin-film solar cells.     

单粒子瞬态脉冲宽度量化与自测试电路设计

为了研究组合逻辑中单粒子瞬态(Single-Event Transient,SET)的特性,采用片上测量技术提出了一套SET脉冲宽度测量方案.针对SET脉冲特性,设计了一种基于自主触发的脉冲测量电路,提出了一种用于自测试验证的脉冲激励电路.基于本所350nm SOI工艺,完成了一款集脉冲收集、测量、自测试于一体的SET重离子辐射测试芯片.通过仿真分析,验证了该方案的有效性.此方案为其他深亚微米工艺下SET研究提供了参考.     

LED日光灯电源内置外卸整体创新设计思考

从技术和市场经济的角度对LED日光灯具的驱动电源设计技术进行分析,说明目前LED灯具长寿命的难点是铝电解电容器本身性能所致,建议革新结构、创新设计LED日光灯可方便内置外卸的驱动电源模块.     

在基于LFSR重播种的压缩环境下同时降低测试数据量和测试功耗

集成电路测试中过高的测试功耗和日益增长的测试数据量是半导体工业面临的两大问题。本文提出了一种在基于线性反馈移位寄存器重播种的压缩环境下基于扫描块的测试向量编码方案。同时,本文也介绍了一种新颖的扫描块重聚类算法。本文的主要贡献是给出了一种灵活的测试应用框架,它能够极大地减少扫描移位期间的跳变个数和经由LFSR重播种生成的确定位的数目。因此,文中方案能够极大地降低测试功耗和测试数据量。在ISCAS’89基准电路上使用Mintest测试集进行的实验表明,本文方法能够减少72%-94%的跳变,并且能获得高达74%-94%的测试压缩率。     

Graphene as interface modifier in ITO and ITO-Cr electrodes

We explore graphene as interface modifier for electrodes in optoelectronic organic devices by measuring the electrical properties of ITO/graphene and ITO/Cr/graphene. For this purpose, exfoliated graphene (EG) was electrochemically synthesized and deposited by spray-pyrolysis. The built-in voltage (Vbi) values were 450 mV for the ITO/CuPc/Al reference, 750 mV for ITO/Cr/graphene/CuPc/Al and 1000 mV for ITO/graphene/CuPc/Al device structures. From these results, we estimate the work functions as 3.20 eV, 3.45 eV and 4.75 eV for ITO/EG, ITO/Cr/EG and ITO. To understand how the work function changes, we carried out first-principles calculations based on density-functional theory (DFT) where Cr work function (~4.2 eV) is not modified by the deposition of pristine graphene; however there is a substantial increase (from 4.2 eV to 5.2 eV), upon deposition of graphene oxide (GO), resulting from a complete transfer of O atoms from the GO sheet to the Cr surface forming a thin layer of chromium oxide.     

Via wearout detection with on-chip monitors

This project aims to detect the onset of chip failure due to via voiding through monitoring the delays of paths in a chip. The proposed method relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The delay increase, as a function of the failure distribution parameters, the path length, gate type, and process variation, has been investigated. An on-chip, ring oscillator-based wearout monitoring circuit is presented. The proposed scheme monitors the delay through a data path using a delay detection circuit (DDC).