一种改进的嵌入式SRAM内建自测试设计

对单端口SRAM常用的13N测试算法进行修改和扩展,提出了一种适用于双端口SRAM的测试算法。该测试算法的复杂度为O(n),具有很好的实用性。作为一个实际应用,通过将该算法和13N测试算法实现于测试算法控制单元,完成了对片内多块单端口SRAM和双端口SRAM的自测试设计。     

A structure and technique for pseudorandom-based testing of sequential circuits

Presented is a register structure and generator design which enables non-scan sequential testing using parallel pseudorandom-based patterns applied to the circuit's primary inputs. The proposed register structure and register control strategy uses the circuit under test's (CUT's) natural sequential activity to periodically alter a register's output bias to a value near 0.5 (i.e. alter the spread of 1's in the output stream). Thus, over time, it is possible to introduce a larger spread circuit states than that normally reachable when parallel pseudorandom-based test patterns are applied to the input lines of a CUT. Using the register modification, a simple hardware generation system can be designed and is suitable for both on-chip and external testing. Experiments indicate that high fault coverage is attainable in a relatively short test time.     

A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes

In this article, a strategy based on the use of intermediate signatures is proposed that enables the exact fault coverage of compact testing schemes to be determined in a feasible computation time. Two models to predict fault simulation time, a fault simulator dependent and independent model, are developed and used by a dynamic programming based algorithm to find the optimal scheduling of the signatures with respect to the total simulation time. Simulation results for both models are then presented demonstrating the feasibility of the proposed strategy.This work was supported in part by grants from the Natural Sciences and Engineering Research Council (NSERC) of Canada, the Canadian Microelectronics Corporation (CMC) and the British Columbia Advanced Systems Institute (B.C. A.S.I.).     

Optimizing error masking in BIST by output data modification

The error masking in conventional built-in self-test schemes is known to be around 2^–m when the output data is compacted in an m-bit multi-input linear feedback shift register. In the recent years, several schemes have been proposed which claim to reduce the error masking in a significant way while maintaining the need for a small overhead. In this paper, a completely new scheme for reducing error masking is proposed. Unlike the previous schemes in the literature, the new scheme is circuit-dependent and uses the concept of output data modification. This concept suggests modifying the original test output sequence before compaction, in order to obtain a new sequence with a reduced error masking probability. It is shown that the output data modification scheme provides a simple trade-off between the desired error masking which could run into (2^1thousands) and the area overhead needed (which would usually be equal to a 16 or 32 bit multi-input linear feedback shift register) for this masking. Finally, a formal proof is presented which establishes that despite circuit-dependency, the proposed scheme will on the average always lead to the desired error masking.     

Design of ICs applying built-in current testing

Built-in Current (BIC) sensors have proven to be very useful in testing static CMOS ICs. In a number of experimental ICs BIC sensors were able to detect small abnormal I _DDQ currents. This paper discusses the design of the circuit under test and Built-in Current (BIC) sensors, which provide: maximum level of defect detectability, minimum impact of BIC sensor on the performance of the circuit under test and minimum area overhead needed for BIC sensors implementation.This research was supported by NSF Grant MIP8822805.     

BIDES: A BIST design expert system

BIDES is an expert system for incorporating BIST into a hardware design that is described in VHDL. Based on the BILBO technique, the BIDES system allocates pseudorandom pattern generators and signature analysis registers to each combinational logic module in a design in such a way that given constraints on testing time and hardware overhead are satisfied. This assignment is performed using the iterative process of regeneration and evaluation of various BIST implementations. In order to effectively perform regeneration, an abstraction hierarchy for a BIST design is introduced and a hierarchical planning technique is employed using this structure. This formulation also leads to an easily modifiable system. Prolog is used for implementing the system.Now with Samsung Electronics, Chase Plaza Bldg. SF, 34–35 Jeong-Dong, Choong-Ku, Seoul, Korea.     

Electroabsorption studies of organic p-i-n solar cells: Increase of the built-in voltage by higher doping concentration in the hole transport layer

The built-in voltage in solar cells has a significant influence on the extraction of photogenerated charge carriers. For small molecule organic solar cells based on the p-i-n structure, we investigate the dependence of the built-in voltage on the work function of both the hole transport layer and the electrode material. The model system investigated here consists of a planar heterojunction with N,N,N′,N′-tetrakis(4-methoxyphenyl)-benzidine (MeO-TPD) as donor and Buckminster Fullerene (C₆₀) as acceptor material. A higher concentration of the dopant C₆₀F₃₆ in the hole transport layer induces a shift of the work function towards the transport level. The resulting increase of the built-in voltage is studied using electroabsorption spectroscopy, measuring the change in absorption (Stark effect) caused by an externally applied electric field. An evaluation of these electroabsorption spectra as a function of the applied DC voltage enables the direct measurement of the built-in voltage. It is also shown that an increased built-in voltage does lead to a larger short-circuit current as well as a larger fill factor.     

A new on-chip digital BIST for analog-to-digital converters

A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminates the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using Mitel CMOS 1.5 μm technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converters or high resolution pipelined analog-to-digital converters. The presented BIST shows satisfactory results for a nine-bit pipe-lined analog-to-digital converter.     

Four different approaches for the measurement of IC surface temperature: application to thermal testing

Silicon die surface temperature can be used to monitor the health state of digital and analogue integrated circuits (IC). In the present paper, four different sensing techniques: scanning thermal microscope, laser reflectometer, laser interferometer and electronic built-in differential temperature sensors are used to measure the temperature at the surface of the same IC containing heat sources (hot spots) that behave as faulty digital gates. The goal of the paper is to describe the techniques as well as to present the performances of these sensing methods for the detection and localisation of hot spots in an IC.     

改进的大规模集成电路测试方法

为了提高大规模集成电路可测性设计（Design For Test,DFT）的故障覆盖率,减少测试时间,通过分析自我测试（Self-Testing Using MISR and Parallel SRSG,STUMPS）方法中的测试机制,找出了其测试效果不理想的原因,提出了改进型的大规模集成电路的测试方法,用C语言编写了故障模拟程序,并且在ISCAS’85标准测试电路上进行了验证。