Short historical review of development of scientific branch “negatronics”

Main stages of development of negatronics are considered in the article. The review is based on the analysis of research results in the branch of creations of negatrons and devices based on negatrons which use various physical effects in gas, vacuum and semiconductors. Merits and demerits of designed negatrons are generalized. Roles of various scientific trends in the area of negatronics are noted.     

A Difference Reference Voltage Buffer for ΔΣ-Converters

An open loop architecture for a reference voltage buffer in -converters is presented to achieve fast-settling, since the settling time of the references plays an important role in the global performance of sampled data converters. This design has been tested on a 2-1 -converter with an on-chip bandgap reference increasing the input related dynamic range up to 93.4 dB for a bandwidth of 99 kHz.     

Current Operational Amplifier (COA): CMOS Realization and Active Compensation

A methodology for analysis and synthesis of lowpass sigma-delta () converters is presented in this paper. This method permits the synthesis of modulators employing continuous-time filters from discrete-time topologies. The analysis method is based on the discretization of a continuous-time model and using a discrete simulator, which is more efficient than an analog simulator. In our analysis approach, the influence of the sample and hold block and non-idealities of the feedback DAC can be systematically modeled by discrete-time systems. Finally, a realistic design of a second-order modulator with a compensation of the non-ideal behavior of the DAC is given. Moreover, simulation results show a good agreement with the theoretical predictions.     

A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs

This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in segmented and binary weighted digital to analog converters (DACs). The BIST scheme comprises of a hierarchy of tests including tests for non-monotonicity, checks to detect if the DNL/INL errors exceed ±0.5 LSB and actual estimation of the DNL/INL. The BIST scheme has been experimentally verified on 10-bit segmented current steering DAC. The DAC, along with the additional circuits required for testing, was designed and fabricated using a 0.35 m process. Both simulation and experimental results are included in this paper. Errors estimated using the BIST scheme match well with measurements done on the fabricated device.     

Adaptive Correction of Errors in Residue Coupled MASH ΔΣ Modulators

MASH delta-sigma () modulators consist of a cascade of several lower order single-loop modulators. In an ideal cascade, the quantization error from all but the last stage are digitally canceled. The drawback with a cascaded design is the requirement of precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta-sigma stages. This paper presents a new, adaptive improvement to the residue coupled MASH delta sigma modulator. The adaptive corrections significantly reduce the sensitivity to analog imperfections. The result is a simple MASH delta-sigma modulator with high precision. Simulations of a 1-1 MASH circuit structure with errors and corrections are included to confirm the theory.     

Buck控制器中仿真电流模式控制电路的设计

论述了一种应用于Buck型开关电源控制器的仿真电流模式控制方法及相应的电路设计。该技术可用于新一代符合VRMIO标准的处理器供电电路。分析了传统电流模式控制在此应用条件下的局限性，提出了利用仿真电流模式实现Buck型开关电源的电流跟踪控制，并分析了电路的工作原理及设计实现。电路采用1．5μm BCD工艺实现。电路与系统的仿真结果表明，所预期的设计要求均已实现。     

基于MCU的锂离子电池管理器设计

锂离子电池对充电器、保护电路的要求比较苛刻,通常要求恒流、恒压的充电方式,而且需要过充、过放保护。为了使锂离子电池安全高效地使用,设计了一种基于Buck变换器的锂离子电池管理器。该管理器采用单片机进行充电控制,通过在程序中运用两个数字PI调节器实现恒流、恒压方式。此外,还用专用保护芯片对电池进行过充、过放等一系列保护。实验结果表明,该管理器不仅满足锂离子电池的充电要求,并且实现对电池的有效保护,达到了管理电池充放电过程的目的。     

电压反馈型DC-DC变换器的稳定性研究

建立了电压反馈型DC-DC变换器连续运行模式下的频闪映射模型，利用离散映射方程的Jacobian矩阵的特征值分析了变换器在参数变化时不动点的失稳情况. 以具体的电压反馈型buck变换器为例， 通过理论分析与数值仿真，两者的结果具有很好的一致性，表明利用离散映射分析DC-DC变换器的稳定性是切实可行的. 关键词： 离散映射模型 DC-DC变换器 稳定性     

Pseudo-V2 control with adaptive compensation for fast-transient current-mode buck converter

A type of pseudo-V² control, with on-chip adaptive compensation to achieve fast transient (FT) response for current mode DC–DC buck converter, has been proposed and simulated using 0.18 μm CMOS technology in this paper. Based on a new on-chip capacitor multiplier, adaptive compensation is achieved by making the compensation capacitance to track the load current. The proposed pseudo-V² control utilizes the output ripple to determine the duty cycle during load transient. Thus the overshoot/undershoot voltage and the transient recovery time are effectively reduced. Simulation results demonstrate the transient ripple is smaller than 50 mV and the transient recovery time is shorter than 10 μs for a 450 mA load current step. The maximum power conversion efficiency is 94.6% at 1 MHz switching frequency when input and output voltages are 5 V and 1.8 V, respectively.     

PWM型DC/DC开关变换器的自抗扰控制策略

文章介绍了自抗扰控制器的原理和结构。结合开关变换器脉动和非线性的特点，介绍了自抗扰控制器在DC—DC开关变换器中的应用；并对具体的Buck电路进行了建模、仿真和实验，结果验证了控制策略的优良性。