三角组列的完全收敛性

设 {Xi,i≥ 1 }为独立同分布的随机变量序列 ,h为 R2→R的实可测函数 .考虑三角组列 un=∑i相似文献   

行为NA的随机变量阵列加权和的Lr收敛性

{Xni,1 i Kn↑∞,n 1}为行为NA的随机变量阵列,{ani,1 i Kn↑∞,n 1}为实数阵列,研究了∑Kni=1aniXni的Lr收敛性.     

Application of Wet Chemical Etching in Fabrication Process of GaAs/AlGaAs Quantum Dot Arrays

Ｌｏｗｄｉｍｅｎｓｉｏｎａｌｓｔｒｕｃｔｕｒｅｓ,ｓｕｃｈａｓｑｕａｎｔｕｍｗｅｌｌ（ＱＷ）,ｑｕａｎｔｕｍｗｉｒｅ（ＱＷＲ）ａｎｄｑｕａｎｔｕｍｄｏｔ（ＱＤ）ｈａｖｅａｔｔｒａｃｔｅｄｍｏｒｅａｎｄｍｏｒｅａｔｔｅｎｔｉ...     

碳纳米管阵列拉曼光谱的对比研究

利用热化学气相沉积技术制备碳纳米管阵列,并对不同工艺下获得的一系列定向碳纳米管阵列进行了拉曼光谱的对比研究。研究发现：碳纳米管阵列一阶拉曼光谱的G峰中心和D峰中心都会向低波数方向发生红移。并且阵列中碳管的一致性、准直性越好,红移的波数就越多。除了谱峰以外,D线和G线的积分强度比I_D / I_G也能够反映所研究的碳材料的有序度和完整性。I_D / I_G越低,说明该碳纳米管阵列的石墨化越好,无定形碳杂质越少。     

FPGA器件设计技术发展综述

现场可编程门阵列(Field Programmable Gate Array,FPGA)作为一种可编程逻辑器件,在短短二十多年里从电子设计的外围器件逐渐演变为数字系统的核心,在计算机硬件、通信、航空航天和汽车电子等诸多领域有着广泛的应用。伴随着半导体工艺技术的进步,FPGA器件的设计技术取得了飞跃性突破。该文在回顾FPGA发展历史的同时,对目前主流FPGA器件的前沿技术进行总结,并对新一代FPGA的发展前景进行展望。     

非制冷微悬臂梁式红外焦平面探测器读出电路设计

针对非制冷微悬臂梁电容式红外探测器,设计了一款焦平面读出电路.根据电路噪声建模与分析,对电路进行了优化设计以抑制噪声.采用0.35μm的CMOS工艺设计,制造了16×16读出电路原型.测试结果表明,5V电源电压、50Hz帧频下电路总功耗为16.5mW,典型工作模式下线性度为99.2%,通道一致性大于97%,等效输入噪声电荷小于150e.     

直接调制半导体激光器的脉冲驱动电路研究

研制了一种应用于直接调制半导体激光器的脉冲驱动电路.根据直接数字频率合成原理,利用现场可编程逻辑阵列产生频率可调方波去触发雪崩晶体管,以及雪崩晶体管的雪崩效应产生频率可调脉宽固定在3 ns的主体脉冲.该脉冲经过衰减器衰减得到合时的脉冲幅度.输出脉冲最高频率可到100 kHz,其输出电压幅度为9 V.     

A note on two measures of dependence

In a paper in 1956, Dobrushin proved a central limit theorem for triangular arrays of Markov chains under certain dependence assumptions somewhat related to “Doeblin’s condition”. In a very recent paper, Peligrad proved a central limit theorem of the same type, but with dependence assumptions based on maximal correlations. This note here will give a concrete example to illustrate the extent to which Peligrad’s result goes beyond that of Dobrushin.     

Hybrid redundancy approach to increase the reliability of FPGA based speed controller core for high speed train

With the progress of the railway technology, the railway transportation is becoming more efficient, intelligent and faster. High speed trains, as a major part of the railway transportation, are engaged with passenger＇s safety, and therefore the reliability issue is very important in such vital systems. In this paper, a dependable speed controller core based on FPGA has been developed for high speed trains. To improve the reliability and mitigate single upset faults on basic speed controller, this paper proposes a new effective method which is based on hardware redundancy. In the proposed Hybrid Dual Duplex Redundancy （HDDR） method, the original controller is quadruplicated and correct values are voted through the comparator and error detection unit. We have analyzed the proposed system with Reliability, Availability, Mean time to failure and Security （RAMS） theory in order to evaluate the effectiveness of proposed scheme. Theoretical analysis shows that the Mean Time To Failure （MTTF） of the proposed system is 2.5 times better than the traditional Triple Modular Redundancy （TMR）. Furthermore, the fault injection experimental results reveal that the capability of tolerating Single Event Upsets （SEUs） in the proposed method increases up to 7.5 times with respect to a regular speed controller.     

NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS简

Field Programmable Gate Arrays （FPGAs） offer high capability in implementing of com- plex systems, and currently are an attractive solution for space system electronics. However, FPGAs are susceptible to radiation induced Single-Event Upsets （SEUs）. To insure reliable operation of FPGA based systems in a harsh radiation environment, various SEU mitigation techniques have been provided In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA. The proposed approach combines the fault injection controller with the host FPGA, and therefore the hardware complexity is minimized. All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.