Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.     

Low-Power Adaptive Biased Integrated Amplifiers

In this paper the author will present the working principle and the applications of a novel adaptive biasing topology, designed to decrease the stand-by power dissipation without affecting the transient performance of low-power amplifiers. The proposed circuit, whose principle and circuit topology can be implemented both in CMOS and in bipolar standard technologies, gives a biasing current whose value depends on the applied input differential voltage and can be set according to the requested transient performance constraints. The adaptive architecture can be utilized in the design of high-efficient low-power operational amplifiers, for the biasing of both the input stage (where the input source current is dynamically increased) and the output stage (where the output current can be controlled and limited). These amplifiers show a very good behaviour, evaluated in terms of two efficiency factors, if compared with those of other adaptive solutions and class-AB topologies, proposed in the literature. Simulation results and also measurements on a chip prototype, fabricated in a standard CMOS technology, are finally presented.     

用于多种组装技术的厚膜导体复合结构

厚膜导体Ｐｄ－Ａｇ／Ａｕ、Ｐｔ－Ｐｄ－Ａｕ／Ａｕ平面复合结构，Ｐｄ－Ａｇ／Ａｕ立体复合结构可使多种组装技术相互兼容。立体复合结构还可有效地降低导体线电阻，减少线损耗。而且，其超声键合性尤佳     

国外模拟IC的发展现状分析

本文主要根据电子整机的发展要求,从集成化、高性能和高可靠等三方面分析国外模似IC的发展,进而说明模拟IC总的发展趋势及其表现。最后指出,模拟IC正面临一个新的变革时期。     

Laser nanosources based on planar photonic crystals as new platforms for nanophotonic devices

Two-dimensional photonic crystal lasers have been fabricated on III–V semiconductor slabs. Tuning of the spontaneous emission in micro and nanocavities has been achieved by accurate control of the slab thickness. Different structures, some of them of new application to photonic crystal lasers, have been fabricated like the Suzuki-phase or the coupled-cavity ring-like resonators. Laser emission has been obtained by pulsed optical pumping. Optical characterization of the lasing modes have been performed showing one or more laser peaks centred around 1.55 μm. Far field characterization of the emission pattern has been realized showing different patterns depending on the geometrical shape of the structures. These kinds of devices may be used as efficient nanolaser sources for optical communications or optical sensors.     

电路板故障诊断中神经网络信息融合技术的应用

将信息融合技术应用到导弹电子设备的电路板故障诊断之中．提出了一种基于红外热成像实验的温度故障隶属度函数构造形式以及改进的BP神经网络算法。进行了BP神经网络信息融合故障诊断的实验研究．从结果看信息融合能较好地解决电路板元件故障诊断的不确定性问题。     

综合网管中基于模型驱动的元数据管理

提出了一种基于模型驱动的元数据管理方案．方案采用了基于模型的形式化描述方法，统一了专业网管子系统间的元数据模式；通过引入模型驱动技术，从元模型的抽象层次消除了不同专业网管子系统之间存在的“信息孤岛”；方案还对综合网管环境下的元数据理论和交换机制进行了研究，并给出了元数据的管理框架以及元数据交换的Java接口映射．     

Memory management optimization problems for integrated circuit simulators

In hardware design, it is necessary to simulate the anticipated behavior of the integrated circuit before it is actually cast in silicon. As simulation procedures are long due to the great number of tests to be performed, optimization of the simulation code is of prime importance. This paper describes two mathematical models for the minimization of the memory access times for a cycle-based simulator.An integrated circuit being viewed as a directed acyclic graph, the problem consists in building a graph order on the vertices, compatible with the relation order induced by the graph, in order to minimize a cost function that represents the memory access time. For both proposed cost functions, we show that the corresponding problems are NP-complete. However, we show that the special cases where the graphs are in-trees or out-trees can be solved in polynomial time.     

红外焦平面器件脉冲驱动电路的小型化设计

代表着红外器件发展的主流方向的红外焦平面器件，其正常工作时需要驱动脉冲信号多达十几路，为了使红外焦平面阵列处于最佳工作状态，就必须设计出相应的驱动电路。提出了一种红外焦平面器件驱动电路的设计方法。该电路具有体积小、功率低及灵活性好等特点，为驱动电路以及成像系统的小型化提供了良好的技术基础。     

交流源作用下介观RLC电路系统量子态随时间的演化

根据量子不变量理论，同时考虑介观电容器极板间电子波函数的耦合作用和电路的耗散,研究介观RLC电路系统在交流电流源作用下动力学的演化过程，并且得到描述系统量子态随时间的演化算符.进一步的分析结果表明，介观RLC电路系统的波函数将由任意的初态演化到一般的压缩态. 关键词： 介观RLC电路 交变电源 不变量理论 时间演化算符