EDA实现的PLD遥控解码电路

介绍了电子设计自动化EDA (ElectricalDesignAutomation)技术的基本特点 ,以红外遥控为例 ,提出了一种PLD (可编程逻辑器件 )解码电路 ,并用ispLSI10 6 0实现 ,该电路原理简单、设计方便、工作可靠 ,可用于以键盘扫描为输入方式的智能仪器中。     

心理素质诊断模型的建立与应用

综合运用国内外多种测量量表对大学生的心理素质进行诊断与测试 ,并应用多元统计分析方法对其心理素质结构主因素进行定量分析 ,在此基础上建立了心理素质诊断模型 ,并运用该模型对实际问题进行了分析 .     

X441对数放大器的原理及其应用

本文主要介绍X441单片对数放大器的基本原理和应用,并列举了一些具体应用电路。     

Parallel feedforward class-AB control circuits for low-voltage bipolar rail-to-rail output stages of operational amplifiers

A new family of class-AB control circuits for bipolar rail-to-rail output stages of operational amplifiers is presented. Step by step, we report the development of five simple class-AB control circuits showing the advantages of using parallel feedforward. The circuits have been designed in such a way that temperature, supply voltage and process parameters have little influence. To test the output stages, one of them has been implemented in a very simple two-stage operational amplifier on a semi-custom chip. Measurements show a bandwidth of 2.5 MHz, a gain of 40 dB, a quiescent current of 23µA and a maximum output current of 250µA. Simulation results of three other simple operational amplifiers with the new class-AB control circuits are shown, which have a higher gain and maximum output current.     

一种提高微电路外壳使用可靠性的方法

简要分析了白瓷双列直插外壳的失效模式和失效机理，并进行了模拟实验，通过对实验结果的分析，提出对成品微电路进行二次电镀能够提高其外壳的使用可靠性。     

开关电流技术：一种新的模拟抽样数据处理方法

开关电流（ＳＩ）技术是一种新的模拟抽样数据处理技术，介绍了开关电流电路的基本单元结构，讨论了目前开关电流技术中存在的问题及其解决方法。对开关电流技术与开关电容技术的一些基本特征进行了比较，ＳＩ技术不仅结构简单，而且与标准ＣＭＯＳ工艺兼容，可望替代开关电容电路。     

混合集成电路激光功能调值技术

本文提出了激光功能微调技术在高精度混合集成电路上的应用，讨论了关键技术问题，并以实例具体说明。该技术的应用为研制高精度混合集成电路开辟了新途径。     

STN—LCD的新进展

STN-LCD采用新的取向层,消除了残象;采用新的驱动波形,消除了串扰;采用二(口恶)烷、卤化物、链烯基、醚和二苯乙炔,改进了液晶料材的性能,使STN-LCD获得高的对比度、快的响应速度、低的驱动电压;采用有源矩阵驱动方法,消除了帧响应,使STN-LCD获得高的对比度、高的亮度及视频响应速度;使用温度跟踪电路,自动跟踪STN-LCD的阀值电压,使STN-LCD获得宽的工作温度。     

模糊数学在电视机故障诊断中的应用

本文介绍了应用模糊数学方法进行计算机辅助诊断电视机的故障原因,这种方法有效性在于建立模型的因果关系正确性和自动搜索范围及速度。     

Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.