H.264便携式实时编解码器的方案探讨

H.264便携式实时编解码器对实时性、功耗等因素有较高的要求,采用硬件编解码器能够有效地解决这些问题.探讨了基于IP核和基于ASIC的方案,重点介绍了几款H.264不同层次上的全功能编解码芯片.     

从FPGA到ASIC的风险与对策

由于FPGA的种种优点,越来越多的电子设计师在初次设计电子产品时选择FPGA来完成电路的prototype设计。然后,再在必要时将prototype设计从FPGA转换成ASIC。在此转换过程中有一定的风险,如ASIC电路的复位、时钟树的设计、封装形式的选择以及可测性设计等。文中讨论了这些风险,并给出了减少这些风险的解决方案。     

A contribution towards model-based design of application-specific MEMS

The design process of heterogeneous systems containing electro-mechanical components and electronic circuits involves expert knowledge, methods, and tools from different engineering domains. Cost-efficient research and development of such heterogeneous systems requires a systematic design flow without gaps. A contribution towards this global goal is presented in this article. A development and synthesis tool for one-dimensional accelerometer MEMS has been implemented, calculating sensor solutions and generating the models and layouts required for a hierarchical design flow in an automatic, module-based approach. Utilizing this flow, different accelerometers have been designed, manufactured, and characterized. A dedicated readout ASIC was developed to validate their dynamic behaviour.     

FPGA and ASIC implementation of robust invisible binary image watermarking algorithm using connectivity preserving criteria

Digital watermarking is the process of hiding information into a digital signal to authenticate the contents of digital data. There are number of watermarking algorithm implemented in software and few in hardware. This paper discusses the implementation of robust invisible binary image watermarking algorithm in Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASIC) using connectivity preserving criteria. The algorithm is processed in spatial domain. The algorithm is prototyped in (i) XILINX FPGA (ii) 130 nm ASIC. The algorithm is tested in Virtex-E (xcv50e-8-cs144) FPGA and implemented in an ASIC.     

BWA系统中判决反馈均衡器的ASIC实现

随着集成电路日新月异的发展,体积和功耗以及实时性要求已经成为衡量集成电路好坏的重要指标.为了克服采用多片通用集成电路实现时,体积和功耗比较大,以及采用DSP实现时不能很好满足实时性的要求,本文针对无线宽带高速数据通信对实时性要求比较高的特点,采用SoC设计的方法,对BWA系统中判决反馈均衡器进行了ASIC实现.通过采用ASIC的实现方法,以及自顶向下的模块设计方法,很好地满足了下一代无线通信判决反馈均衡器对实时性要求,同时也满足了功耗和性能的要求.     

A rapid turnaround design of a high speed VLSI search processor

Performance of relational database systems is a major impediment to their use in many applications. We have designed and implemented a customized RISC processor to accelerate associative search and aggregation operations for relational database systems. Since the processor is programmable and supports many queries concurrently, a system utilizing tens of such processors is capable of handling thousands of complex search requests simultaneously.

While the design of a VLSI programmable processor is a complex process, research prototyping requires a fast turnaround design process. We took advantage of the logic programming paradigm and the silicon compiler technology to explore and simulate architecture alternatives prior to the actual implementation. The prototyping process allowed us to complete the chip design in nine months. The resulting processor, fabricated in 2 Itm CMOS technology, consists of 91,000 transistors, executes over 18 million predicate evaluations per second, and searches database contents at 74 megabytes per second.     

自指针先入先出电路设计的研究

本文给出一种特殊的自指针先入先出(FIFO)电路的设计。其优点是结构简单，避免了额外的寻址指针处理，然而又同样能完成异步读／写所需的指针操作。采用电子CAD技术进行仿真的结果表明电路实现了预定的功能，可用于各种需要对数据流实施速率调整的电子信息系统中。     

60 Gbit/s宽带电路交换ASIC芯片设计

文章提出了一种60 Gbit/s宽带电路交换专用集成电路(ASIC)芯片的设计实现方案.针对设计芯片速度快、规模大和功耗大等特点,给出了采用流水线设计思想和优化结构处理技术的电路设计解决方案.同时还给出了采用现场可编程门阵列(FPGA)芯片对设计电路进行功能验证的结果和ASIC流片的基本数据.     

高速序列密码算法芯片设计技术

论文介绍了序列密码算法芯片的基本结构,提出了高速序列密码算法芯片的实现技术,并通过实际芯片的设计证明了方法的有效性。     

16位稳态电流LED驱动器的ASIC设计

提出了一种大电流16位稳态电流LED驱动器的ASIC设计方案,并描述了芯片的主要功能原理。对各个模块的主要电路进行了分析和设计,数字部分电路依靠成熟的FPGA平台验证,最大程度提高了电路可靠性;模拟部分电路通过分析和计算,确定不同参数,最后对整个方案进行了仿真。这种16位稳态电流LED驱动芯片可以完成对点阵LED显示屏的驱动,芯片外围电路简单、成本低、可靠性高。该芯片也适用于点阵LED屏等LED设备的驱动,应用十分广泛。芯片方案的各个部分都给出了详细的仿真结果,整个方案最后通过了T-Spice后仿真。