重新播种的测试方法研究

重新播种的测试方法是一种内建自测试方法,它可以用来提高伪随机测试矢量的故障覆盖率。介绍了 三种重新播种的测试方法,它们分别是使用很少种子的内建自测试重新播种方法、多重多项式线性反馈移位寄存器 的重新播种方法和使用部分线性反馈移位寄存器的重新播种方法。这三种方法在测试的硬件开销方面或在编码效率 等方面有所改进。     

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST

In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inverting the logic value of some of the bits of the next state of the Test Pattern Generator (TPG). The proposed reseeding technique is generic and can be applied to TPGs based on both Linear Feedback Shift Registers (LFSRs) and accumulators. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and allows to well exploiting the trade-off between hardware overhead and test length. Using experimental results we show that the proposed method compares favorably to the other already known techniques with respect to test length and the hardware implementation cost.     

On Using Twisted-Ring Counters for Test Set Embedding in BIST

We present a novel built-in self-test (BIST) architecture for high-performance circuits. The proposed approach is especially suitable for embedding precomputed test sets for core-based systems since it does not require a structural model of the circuit, either for fault simulation or for test generation. It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for high-performance designs because it does not add any mapping logic to critical functional paths. Test patterns are generated on-chip by carefully reseeding the TRC. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits.Instead of being stored on-chip, the seed patterns can also be scanned in using a low-cost, slower tester. The seeds can be viewed as an encoded version of the test set that is stored in tester memory. This requires almost 10X less memory than compacted test sets obtained from ATPG programs. This allows us to effectively combine high-quality BIST with external testing using slow testers. As the cost of high-speed testers increases, methodologies that facilitate testing using slow testers become especially important. The proposed approach is a step in that direction.     

基于变周期重播种LFSR的测试生成

基于重播种的LFSR结构的伪随机测试生成中包含的冗余测试序列较多,因而其测试序列长度仍较长,耗费测试时间长,测试效率不高。针对此状况,提出基于变周期重播种的LFSR结构的测试生成方法。该方法可以有效地跳过伪随机测试生成中的大量冗余测试序列。在保证电路测试故障覆盖率不变的条件下,缩短总测试序列的长度。分析结果表明,同定长重播种方法相比,该方法能以较少的硬件开销实现测试序列的精简,加快了测试的速度,提高了电路测试诊断的效率。     

重新播种的测试方法研究

重新播种的测试方法是一种内建自测试方法，它可以用来提高伪随机测试矢量的故障覆盖率。介绍了三种重新播种的测试方法，它们分别是使用很少种子的内建自测试重新播种方法、多重多项式线性反馈移位寄存器的重新播种方法和使用部分线性反馈移位寄存器的重新播种方法。这三种方法在测试的硬件开销方面或在编码效率等方面有所改进。     

An effective logic BIST scheme based on LFSR-reseeding and TVAC

An effective logic built-in self-test scheme aiming at reducing the area overhead of IC testing and improving the fault average is proposed, which combines strategies of linear feedback shift register (LFSR)-reseeding with test vectors applied by circuit-under-test itself (TVAC). LFSR-reseeding technology is first applied to decrease the size of test set and the number of interior feedback wires, while TVAC technology is applied to decrease the number of stored seeds. An efficient LFSR-reseeding algorithm and a modified quick judgment method for path search are proposed. Experimental results for ISCAS 85 benchmarks demonstrate that the proposed method reduces the number of interior feedback wires more than 50% on average and can achieve full fault coverage with much less groups as well as area overhead compared with previous TVACs.     

Reducing test-data volume and test-power simultaneously in LFSR reseeding-based compression environment

This paper presents a new test scheme based on scan block encoding in a linear feedback shift register (LFSR) reseeding-based compression environment.Meanwhile,our paper also introduces a novel algorithm of scan-block clustering.The main contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during scan shift and the number of specified bits that need to be generated via LFSR reseeding.Thus,it can significantly reduce the test power and test data volume.Experimental results using Mintest test set on the larger ISCAS’89 benchmarks show that the proposed method reduces the switching activity significantly by 72%-94%and provides a best possible test compression of 74%-94%with little hardware overhead.