8VSB芯片的层次式设计方法

提出了深亚微米下系统级芯片层次式版图设计的方法，并用该方法设计了HDTV信道解码芯片8VSB的版图。实例设计结果表明，该方法在节约面积、加速时序收敛方面效果明显，大大缩短了芯片设计周期。     

用TMS320C6201实现H.263编译码系统

介绍了用TMS320C6201实现视频压缩编码标准H.263的编译码系统,并以编码系统为例,给出其硬件设计及软件的优化处理方法.     

基于HOP的可调光编码／解码器的研究

提出了一种基于全息光处理器的可调光编码/解码器的实现方案。全息光处理器可以在空间进行编/解码，每个通信网络单元可以采用任意速率的数字或模拟的调制信号，它非常适合于多媒体的通信网络环境，通过对全息光处理器的折射率大小和位置的控制，当一个输入光脉冲经过光处理器中具有特定折射率的空间位置后，便可在处理器的输出端口得到合适的输出信号。本文给出了这种基于全息光处理器的可调光编码/解码器的仿真实验，结果是可行的，与以前文献中提出的结构相比，减小了硬件实现的复杂性，降低了成本和功耗，便于集成。     

Atmospheric and low pressure shadow masked MOVPE growth of InGaAs(P)/InP and (In)GaAs/(Al)GaAs heterostructures and quantum wells

The shadow masked growth technique is presented as a tool to achieve thickness and bandgap variations laterally over the substrate during metalorganic vapor phase epitaxy. Lateral thickness and bandgap variations are very important for the fabrication of photonic integrated circuits, where several passive and active optical components need to be integrated on the same substrate. Several aspects of the shadow masked growth are characterized for InP based materials as well as for GaAs based materials. Thickness reductions are studied as a function of the mask dimensions, the reactor pressure, the orientation of the masked channels and the undercutting of the mask. The thickness reduction is strongly influenced by the mask dimensions and the reactor pressure, while the influence of the orientation of the channels and the amount of undercutting is only significant for narrow mask windows. During shadow masked growth, there are not only thickness variations but also compositional variations. Therefore, we studied the changes in In/Ga and As/P ratios for InGaAs and InGaAsP layers. It appears that mainly the In/Ga-ratio is responsible for compositional changes and that the As/P-ratio remains unchanged during shadow masked growth.     

光纤码分多址技术在城域接入网中的应用

分析了光纤码分多址技术O -CDMA在城域接入网中的应用。回顾了O -CDMA技术的发展历史 ,详细地介绍了O -CDMA技术的特点 ,其具有的公平性、灵活性、网络控制管理、对服务区处理能力以及高的安全性使O -CDMA技术成为较好的城域接入网技术。阐述了目前在应用中O -CDMA存在的一些技术方面的问题     

SDI接口数字监视设备的设计与实现

介绍了一种对SDV(串行数字视频)信号进行解码的设备设计方案，提出了该系统的总体构架，并对该系统的硬件设计、软件设计进行了全面的论述。设计的产品具有较高的性能价格比，已进入了推广阶段。     

一种高资源效率的Fast-RCSC极化码译码器

针对现有极化码软输出译码器存在的高资源消耗与低资源效率,设计了一种快速低复杂度软取消(Fast Reduced Complexity Soft-Cancelation,Fast-RCSC)译码算法及其译码器硬件架构。Fast-RCSC算法对内部特殊结点进行完整计算,在减少译码周期的同时仍有较好译码性能。基于不同特殊结点公式之间存在相似性,进而通过对引入的特殊结点模块进行计算结果复用以及计算模块分时复用,减少特殊结点模块资源消耗。通过共用存储单元以及对不足存储单元数据宽度的数据进行合并,降低存储资源消耗。在华润上华(Central Semiconductor Manufacturing Corporation,CSMC)180nm工艺下综合结果表明,设计的译码器在码长为1024的情况下,面积为2.92mm²,资源效率为245.2Mbps/mm²,相比现有软输出译码器有不同程度的提升。     

Least squares decoding in binomial frequency division multiplexing

This paper proposes a method that can reduce the complexity of a system matrix by analyzing the characteristics of a pseudoinverse matrix to receive a binomial frequency division multiplexing (BFDM) signal and decode it using the least squares (LS) method. The system matrix of BFDM can be expressed as a band matrix, and as this matrix contains many zeros, its amount of calculation when generating a transmission signal is quite small. The LS solution can be obtained by multiplying the received signal by the pseudoinverse matrix of the system matrix. The singular value decomposition of the system matrix indicates that the pseudoinverse matrix is a band matrix. The signal-to-interference ratio is obtained from their eigenvalues. Meanwhile, entries that do not contribute to signal generation are erased to enhance calculation efficiency. We decode the received signal using the pseudoinverse matrix and the removed pseudoinverse matrix to obtain the bit error rate performance and to analyze the difference.     

基于SSCANL译码器的联合迭代检测译码算法

为了提升基于极化码的稀疏码多址接入（sparse code multiple access,SCMA）系统接收机性能,提出了基于简化软消除列表（simplify soft cancellation list,SSCANL）译码器的循环冗余校验（cyclic redundancy check,CRC）辅助联合迭代检测译码接收机方案。该方案中极化码译码器使用SSCANL译码算法,采用译码节点删除技术对软消除列表（soft cancellation list,SCANL）算法所需要的L次软消除译码（soft cancellation, SCAN）进行简化,通过近似删除冻结位节点,简化节点间软信息更新计算过程,从而降低译码算法的计算复杂度。仿真结果表明,SSCANL算法可获得与SCANL算法一致的性能,其计算复杂度与SCANL算法相比有所降低,码率越低,算法复杂度降低效果越好;且基于SSCANL译码器的CRC 辅助联合迭代检测译码接收机方案相较基于SCAN译码器的联合迭代检测译码（joint iterative detection and decoding based on SCAN decoder, JIDD-SCAN）方案、基于SCAN译码器的CRC辅助联合迭代检测译码（CRC aided joint iterative detection and decoding based on SCAN decoder,C-JIDD-SCAN）方案,在误码率为10^-4时,性能分别提升了约0.65 dB、0.59 dB。     

12bit 800MSPS电流舵结构的高速DAC设计

本文设计了一个分辨率为12位，采样频率为800MHz的高速电流舵结构DAC。该设计基于TSMC0．18umCMOS工艺，采用了二进制码控制和温度计码译码控制相结合的方式，从而在降低DNL误差和减小毛刺的同时，又能实现较小的芯片面积和功耗。为达到高的精度和高的转换速度，该设计在系统结构、电路结构以及芯片版图等方面都做了优化。