Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel low-density metal-oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage(BV) for an ultra-high-voltage(UHV) high-side thin layer silicon-on-insulator(SOI) p-channel lateral double-diffused metal-oxide semiconductor(LDMOS).Compared with the conventional simulation method,the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit.The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method.Simulation results show that the off-state(on-state) BV of the SOI p-channel LDMOS can reach 741(620) V in the 3-μm-thick buried oxide layer,50-μm-length drift region,and at 400 V back-gate voltage,enabling the device to be used in a 400 V UHV integrated circuit.     

The research on suspended ZnO nanowire field-effect transistor

This paper reports that a novel type of suspended ZnO nanowire field-effect transistors (FETs) were successfully fabricated using a photolithography process, and their electrical properties were characterized by I--V measurements. Single-crystalline ZnO nanowires were synthesized by a hydrothermal method, they were used as a suspended ZnO nanowire channel of back-gate field-effect transistors (FET). The fabricated suspended nanowire FETs showed a p-channel depletion mode, exhibited high on--off current ratio of ～10⁵. When V_DS=2.5 V, the peak transconductances of the suspended FETs were 0.396 μS, the oxide capacitance was found to be 1.547 fF, the pinch-off voltage V_TH was about 0.6 V, the electron mobility was on average 50.17 cm²/Vs. The resistivity of the ZnO nanowire channel was estimated to be 0.96× 10²Ω cm at V_GS = 0 V. These characteristics revealed that the suspended nanowire FET fabricated by the photolithography process had excellent performance. Better contacts between the ZnO nanowire and metal electrodes could be improved through annealing and metal deposition using a focused ion beam.     

Robust FinFET SRAM design based on dynamic back-gate voltage adjustment

In this paper, we propose a robust SRAM design which is based on FinFETs. The design is performed by dynamically adjusting the back-gate voltages of pull-up transistors. For the write operation, we use an extra write driver which sets the desired back-gate voltages during this operation. This approach considerably increases the write margin. During the hold state, the back-gates are precharged to the supply voltage using an extra precharge circuit. This decreases the static power. Finally, we use nMOS switches to provide the optimum back-gate voltages during the read state. To minimize the area and power overheads, an instance of the circuitry is used for each column. The performance of the proposed technique is assessed using mixed mode device/circuit simulations for a physical gate length of 22 nm. The results show that the minimum operating voltage for six-sigma read and write yield is about 0.15 V lower than that of the recently proposed structures. In addition, the suggested SRAM shows significantly higher write margin and lower static power compared to the recently proposed structures. The minimum operating voltage of our proposed structure can be lowered down to 0.5 V through some work function tuning to balance the read and write stability. This minimum voltage is 0.1 V lower than the minimum operating voltage of the other structures with similar work function tunings.     

SOI LDMOSFET的背栅特性

在绝缘体上硅衬底上,制备了栅长为0.5μm的低势垒体接触结构和源体紧密接触结构的横向双扩散功率晶体管.详细研究了器件的背栅特性.背栅偏置电压对横向双扩散功率晶体管的前栅亚阈值特性、导通电阻和关态击穿特性均有明显影响.相比于源体紧密接触结构,低势垒体接触结构横向双扩散功率晶体管的背栅效应更小,这是因为低势垒体接触结构更好地抑制了浮体效应和背栅沟道开启.还介绍了一种绝缘体上硅横向双扩散功率晶体管的电路模型,其包含前栅沟道,背栅沟道和背栅偏置决定的串联电阻.     

Highly stable,low power FinFET SRAM cells with exploiting dynamic back-gate biasing

In this paper, we propose two independent gate (IG) FinFET SRAM cells that use PMOS access transistors and back-gate (BG) biasing to achieve a high-stability performance. In the first cell, the back-gate of the access transistors is connected to the adjacent storage nodes, and the back-gate of the pull-down transistors is dynamically biased. Simulations indicate that the first proposed cell offers higher read static noise-margin (SNM), higher write-ability, least static/dynamic power, and a comparable read current compared to the previous IG-6TSRAMs. The second cell is a novel independently-controlled-gate FinFET SRAM cell, which provides a high read stability, the highest write-ability, low static power dissipation and high read current compared to the previously reported independently-controlled-gate FinFET SchmitTrigger based SRAM cells. This cell supportsbit-interleaving property at V_DD = 0.4 V with high read/write yields.     

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel lateral double-diffused metal\ben oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage (BV) for an ultra-high-voltage (UHV) high-side thin layer silicon-on-insulator (SOI) p-channel low-density metal-oxide semiconductor (LDMOS). Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state (on-state) BV of the SOI p-channel LDMOS can reach 741 (620) V in the 3-μm-thick buried oxide layer, 50-μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.     

Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.     

Fabrication and photoelectrical characteristics of ZnO nanowire field-effect transistors

rease by almost half of the source-drain current (Ids, from 560 nA to 320 nA) due to drain-induced barrier lowering.Continued work is underway to reveal the intrinsic properties of suspended ZnO nanowires and to explore their device applications.     

单壁碳纳米管随机网络场效应晶体管

使用超声分散CVD法合成的商用单壁碳纳米管(SWCNT),利用匀胶机把分散获得的、含有SWCNT的悬浮液均匀旋涂于SiO2/Si基上,利用萌罩式电子束蒸发技术在碳纳米管随机网络薄膜表面制备漏源Au电极。该制备技术避免了碳纳米管器件更多的化学接触,有效确保碳纳米管的纯度。该碳纳米管场效应晶体管器件采用重掺杂Si作为背栅、SWCNT随机网络薄膜为导电沟道。在室温环境下利用Keithley-4200对器件性能进行了测试分析,器件开启电流约为1μA,峰值跨导为326nS。该方法制备的SWCNT随机网络场效应晶体管,具有工艺实现简单、器件性能稳定、重复性和一致性好等特点,并可以用于构建CNT逻辑电路。该技术对于研究低成本、大规模基于CNT的集成电路来说,具有较高的借鉴价值。     

辐照下背栅偏置对部分耗尽型绝缘层上硅器件背栅效应影响及机理分析

基于部分耗尽型绝缘层上硅（SOI）器件的能带结构,从电荷堆积机理的电场因素入手,为改善辐照条件下背栅Si/SiO₂界面的电场分布,将半导体金属氧化物（MOS）器件和平板电容模型相结合,建立了背栅偏置模型.为验证模型,利用合金烧结法将背栅引出加负偏置,对NMOS和PMOS进行辐照试验,得出:NMOS背栅接负压,可消除背栅效应对器件性能的影响,改善器件的前栅I-V特性;而PMOS背栅接负压,则会使器件的前栅I-V性能恶化.因此,在利用背栅偏置技术改善SOI/NMOS器件性能的同时,也需要考虑背栅偏置对PMOS的影响,折中选取偏置电压.该研究结果为辐照条件下部分耗尽型SOI/MOS器件背栅效应的改善提供了设计加固方案,也为宇航级集成电路设计和制造提供了理论支持.