数字化正弦平方脉冲信号

依据正弦平方脉冲的数学方程及其频谱分布，分别导出了与理想和标称视频带宽相对应的正弦平方脉冲的数学表达式及其编程生成方法。实验表明，此法不仅精确，而且便于修改参数，并可直接读人数字电视系统，来测定视频线性响应。     

Multiple Scan Chain Design for Two-Pattern Testing

Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.     

软件集成测试技术研究

首先分析了集成测试的原理和特点，并指出了集成测试的重要性。然后结合传统软件与面向对象软件开发的方法和技术，详细介绍了传统软件的集成测试方法和策略，并深入分析了面向对象软件集成测试的原理和方法。     

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.     

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.     

可靠性试验样本量和截尾时间的计算

可靠性寿命试验中，一般都因受到费用和时间的限制，因此要用截尾试验获得信息，再据此对其可靠性进行统计推断，用非参数估计的方法探讨了进行可靠性试验的样本量或截尾时间的估计方法。     

氪灯和氙灯光谱强度分布和光谱效率测量

氪灯、氙灯光谱强度分布和光谱效率测量是反映氪灯、氙灯性能的关键指标。介绍了一套新型的氪灯、氙灯光谱强度分布和光谱效率检测系统。该系统是一套测量连续发光灯和脉冲闪光灯发光性能及效果的综合检测设备。该检测单元采用计算机进行操控,人机界面良好,便于检验人员进行氪灯和氙灯光谱强度分布和光谱效率的批量检测。检验人员利用该系统可进行装机模拟试验和可靠性试验,可对氪灯和氙灯的性能进行必要的分析研究,不断地积累了氪灯和氙灯的检验数据和经验。     

A simple electronic speckle shearing interferometer

A new speckle shearing interferometer with simple setup is proposed. The interferometer can be converted easily from a speckle referenced speckle pattern interferometer into a speckle shearing interferometer and vice versa. A beamsplitter and a mirror are used to generate the shear. The amount of shear can be adjusted by simply rotating the mirror. The costs involved are low and it is particularly useful for fast inspection in non-destructive testing of structural integrity. Both the theoretical studies of the method of measurement and the experimental results are presented.     

Statistical Inference with Fractional Brownian Motion

We give a test between two complex hypothesis; namely we test whether a fractional Brownian motion (fBm) has a linear trend against a certain non-linear trend. We study some related questions, like goodness-of-fit test and volatility estimation in these models.     

像管亮度增益与背景测试仪

论述像管亮度增益与背景测试仪的原理，介绍仪器的组成以及测试数据的处理方法。