A Comparative Study on Dynamic and Static Sparsity Patterns in Parallel Sparse Approximate Inverse Preconditioning

Sparse approximate inverse (SAI) techniques have recently emerged as a new class of parallel preconditioning techniques for solving large sparse linear systems on high performance computers. The choice of the sparsity pattern of the SAI matrix is probably the most important step in constructing an SAI preconditioner. Both dynamic and static sparsity pattern selection approaches have been proposed by researchers. Through a few numerical experiments, we conduct a comparable study on the properties and performance of the SAI preconditioners using the different sparsity patterns for solving some sparse linear systems. This revised version was published online in July 2006 with corrections to the Cover Date.     

Prime divisors of sparse integers

We obtain a lower bound on the number of prime divisors of integers whose g-ary expansion contains a fixed number of nonzero digits. This revised version was published online in August 2006 with corrections to the Cover Date.     

Hölderian Invariance Principle for Triangular Arrays of Random Variables

In this paper, we extend the Hölderian invariance principle of Lamperti [6] to the case of partial-sum processes based on a triangular array of row-wise independent random variables. As an application, we obtain necessary and sufficient conditions for the almost sure (resp. in probability) weak Hölder convergence of partial-sum processes based on bootstrapped samples.     

Prefiltration technique via aggregation for constructing low‐density high‐quality factorized sparse approximate inverse preconditionings

This paper considers a new approach to a priori sparsification of the sparsity pattern of the factorized approximate inverses (FSAI) preconditioner using the so‐called vector aggregation technique. The suggested approach consists in construction of the FSAI preconditioner to the aggregated matrix with a prescribed sparsity pattern. Then small entries of the computed ‘aggregated’ FSAI preconditioning matrix are dropped, and the resulting pointwise sparsity pattern is used to construct the low‐density block sparsity pattern of the FSAI preconditioning matrix to the original matrix. This approach allows to minimize (sometimes significantly) the construction costs of low‐density high‐quality FSAI preconditioners. Numerical results with sample matrices from structural mechanics and thin shell problems are presented. Copyright © 2002 John Wiley & Sons, Ltd.     

正交试验设计在麦白霉素高产菌株选育中的应用

本文应用正交试验设计改进了麦白霉素的生产工艺，在四个关键环节上选出了比对照组高出７００μ／ｍｌ以上的高产稳定菌株。该法使试验次数减少，选育周期缩短，既节省了人力物力和降低了生产成本，又增加了麦白霉素药粉的产量，取得了可观的经济效益。     

一项从CAA到CAD的工作 ～正交优化法与SPICE相结合

电子电路的计算机辅助设计方法是促进电子技术发展的一种有效工具。本文介绍如何将行之有效的正交优化法与国际盛行的模拟电子电路的分析程序ＳＰＩＣＥ相结合，形成了ＡＣＯＤ软件，将ＣＡＡ扩展为ＣＡＤ。     

Central limit theorem for quadratic forms for sparse tables

Sufficient conditions for asymptotic normality for quadratic forms in {n_t − np_t} are given, where {n_t} are the observed counts with expected cell means {np_t}. The main result is used to derive asymptotic distributions of many statistics including the Pearson's chi-square.     

Numerical analysis for factorial data analysis. Part II: Special purpose hardware—the programmable systolic array SARDA

The second part of this paper deals with the systolic implementation of the computational kernel for factorial data analysis, defined in Part I, on special-purpose hardware. The framework of the study is that a sequence of different algorithms has to be performed on a unique hardware array. This fact has led us to the design of the programmable systolic array SARDA: this is a triangular array which consists of programmable nodes with local memory and programmable orthogonal connections.     

曲面相机阵列多分辨成像方法

针对现有成像系统因数据冗余而无法兼顾大视场、高分辨、高效性的问题,结合人眼视网膜变分辨成像和并列式复眼成像原理,设计一种多分辨率成像的复合仿生成像系统.该成像系统按照球面和平面兼顾的曲面布局方式,利用11个相机镜头构建相机阵列,组成了四个等级分辨率的子眼拍摄模块.通过物距100 m的远景实验和物距10 m的近景实验发现,该系统在实现高分辨成像的同时,获得总视场达150.8°×37.8°.多分辨率成像实验结果表明,该系统获取的图像的分辨率从中心视场到边缘视场逐渐降低,并且相较于中心清晰全视场成像,四级分辨率成像的拼接图像数据量减少了17.2倍的数据冗余.     

用于SCA ASIC测试的数字读出模块设计

高速开关电容阵列(SCA)具有高速采样、低功耗的特点,基于SCA的高速波形数字化是目前高精度时间测量的一个重要研究方向。为此,我们开展SCA芯片的研究,目前已设计完成原型ASIC设计,并正在进行后续版本的改进设计。为便于未来多版本ASIC的测试和评估,需设计具有一定通用性的数字读出模块,本论文工作主要介绍此模块的设计工作以及相应的数据读出软件。数字读出模块基于FPGA实现对待测ASIC的控制、配置及数据读出,采用DDR3片外存储芯片,使用USB3.0等接口进行数据传输;上位机软件基于Python3.7设计,实现了数据采集与波形绘制等功能。目前已使用设计完成的数字读出模块对第2版SCA ASIC进行了初步的测试,测试结果表明,此读出模块工作正常,且SCA芯片输出结果符合预期。