High-temperature growth of very high germanium content SiGe virtual substrates

We have first of all studied (in reduced pressure–chemical vapour deposition) the high-temperature growth kinetics of SiGe in the 0–100% Ge concentration range. We have then grown very high Ge content (55–100%) SiGe virtual substrates at 850 °C. We have focused on the impact of the final Ge concentration on the SiGe virtual substrates’ structural properties. Polished Si_0.5Ge_0.5 virtual substrates were used as templates for the growth of the high Ge concentration part of such stacks, in order to minimize the severe surface roughening occurring when ramping up the Ge concentration. The macroscopic degree of strain relaxation increases from 99% up to values close to 104% as the Ge concentration of our SiGe virtual substrates increases from 50% up to 100% (discrepancies in-between the thermal expansion coefficients of Si and SiGe). The surface root mean square roughness increases when the Ge concentration increases, reaching values close to 20 nm for 100% of Ge. Finally, the field (the pile-up) threading dislocations density (TDD) decreases as the Ge concentration increases, from 4×10⁵ cm⁻² (1–2×10⁵ cm⁻²) for [Ge]=50% down to slightly more than 1×10⁵ cm⁻² (a few 10⁴ cm⁻²) for [Ge]=88%. For [Ge]=100%, the field TDD is of the order of 3×10⁶ cm⁻², however.     

Suppression of boron segregation by interface Ge atoms at SiGe/SiO2 interface

We investigate the migration pathway and barrier for B diffusion at SiGe/SiO₂ interface through first-principles density functional calculations. Similar to the diffusion mechanism reported for Si/SiO₂ interface, a substitutional B, which initially forms a B-self-interstitial complex in SiGe, diffuses to the interface and then to the oxide in form of an interstitial B. At the defect-free interface, where bridging O atoms are inserted to remove interface dangling bonds, it is energetically more favorable for the interstitial B to intervene in the Ge–O bridge bond rather than the Si–O bridge bond at the interface. As a result of the B intervention, interface Ge atoms significantly enhance the stability of B-related defects in the interface region and thereby act as traps for B dopants. At the interface with the Ge–O bridge bond, the overall migration barrier for B diffusion from SiGe to SiO₂ is estimated to be about 3.7 eV, much higher than the reported value of about 2.1 eV at Si/SiO₂ interface. Our results provide a clue to understanding the experimental observation that B segregation toward the oxide is suppressed in SiGe/SiO₂ interface.     

锗硅异质结双极晶体管单粒子效应加固设计与仿真

本文设计了一种通过在版图布局中引入伪集电极的方法来提高锗硅异质结双极晶体管(SiGe HBT)抗单粒子性能的方法. 利用半导体器件模拟工具, 针对加固前后的SiGe HBT开展了单粒子效应仿真模拟, 分析了伪集电极对SiGe HBT电荷收集机理的影响. 结果表明, 引入的伪集电极形成的新的集电极-衬底结具有较大的反偏能力, 加固后SiGe HBT伪集电极通过扩散机理, 大量收集单粒子效应产生的电荷, 有效地减少了实际集电极的电荷收集量, 发射极、基极电荷收集量也有不同程度的降低, 加固设计后SiGe HBT 的单粒子效应敏感区域缩小, 有效的提高了SiGe HBT 器件抗单粒子效应辐射性能. 此项工作的开展为SiGe HBT电路级单粒子效应抗辐射加固设计打下良好的基础.     

Low pitch LWIR QWIPs: Performance level and image quality

We present recent results obtained on 15 μm pitch LWIR QWIP arrays at Sofradir. Based on experimental data gathered on several QWIP wafers, the performance (NETD) at the system level has been estimated. We show that, in spite of the small pitch, values as low as 50 mK can be achieved for rather closed optical systems (f/2.5) and for operating temperatures (74 K) compatible with available compact cryo-coolers.We also demonstrate that specific pixel configurations can be designed to investigate the pixel-to-pixel optical crosstalk. Such measurements can help to better understand the limitations set by the geometry of the pixel on the Modulation Transfer Function (MTF). In particular, we show that the optical crosstalk due to photon transfer through the inter-pixel space is rather small for unthinned devices.     

Impact of amorphous Ge thin layer at the amorphous Si/Al interface on Al-induced crystallization

We investigated the impact of an amorphous Ge (a-Ge) thin layer inserted at the amorphous Si (a-Si)/Al interface on Al-induced crystallization. In situ observation of the growth process clarified that the nucleation rate is drastically reduced by insertion of a-Ge, which led to increase in the average size of crystal grains. This was interpreted as resulting from decrease in the driving force of crystallization, mainly due to the larger solubility of Ge in Al than that of Si in Al. The obtained films were SiGe alloys with lateral distribution of Ge content, and its origin is discussed based on the two-step nucleation process.     

应变SiGe p 型金属氧化物半导体场效应管栅电容特性研究

由于台阶的出现, 应变SiGe p型金属氧化物半导体场效应管 (pMOSFET) 的栅电容特性与体Si器件的相比呈现出很大的不同, 且受沟道掺杂的影响严重. 本文在研究应变SiGe pMOSFET器件的工作机理及其栅电容C-V 特性中台阶形成机理的基础上, 通过求解器件不同工作状态下的电荷分布, 建立了应变SiGe pMOSFET栅电容模型, 探讨了沟道掺杂浓度对台阶的影响. 与实验数据的对比结果表明, 所建立模型能准确反映应变SiGe pMOSFET器件的栅电容特性, 验证了模型的正确性. 该理论为Si基应变金属氧化物半导体(MOS)器件的设计制造提供了重要的指导作用, 并已成功应用于Si基应变器件模型参数提取软件中, 为Si基应变MOS的仿真奠定了理论基础. 关键词： 应变SiGe pMOSFET 栅电容特性 台阶效应 沟道掺杂     

小尺寸应变Si nMOSFET物理模型的研究

本文运用高斯定律得出多晶SiGe栅应变Si nMOSFET的准二维阈值电压模型,并从电流密度方程出发建立了小尺寸应变Si nMOS器件的I-V特性模型.对所得模型进行计算分析,得出沟道Ge组分、多晶Si_1-yGe_y栅Ge组分、栅氧化层厚度、应变Si层厚度、栅长以及掺杂浓度对阈值电压的影响.运用二维器件模拟器对器件表面势和I-V特性进行了仿真,所得结果与模型仿真结果一致,从而证明了模型的正确性. 关键词： 多晶SiGe栅 高斯定理 阈值电压 速度过冲     

Room-temperature SiGe light-emitting diodes

In the present paper the electroluminescence of PIN diodes with either strained SiGe/Si or Ge islands in the i-region has been investigated experimentally and by quantitative modelling. The modelling helped to improve the diode structure. Consequently, diodes with strained Si_0.80Ge_0.20 could be improved so as to reveal emission up to room temperature, if the thickness was high enough. To overcome the thickness limitation due to plastic relaxation, we used selective epitaxy on small areas. We also present results for diodes with Ge islands in the active region. The internal quantum efficiency of light emitting diodes with strained SiGe was at room temperature 10⁻⁴, while diodes with islands emitted ten times less light.     

D波段功率放大器设计

基于0.13 m SiGe BiCMOS工艺, 研究和设计了一种D波段功率放大器芯片。该放大器芯片用了四个功率放大器单元和两个T型结网络构成。功率放大器单元采用了三级的cascode电路结构。低损耗的片上T型结网络既能起到片上功率合成/分配的功能, 又能对输入输出进行阻抗匹配。对电路结构进行了设计、流片验证和测试。采用微组装工艺将该芯片封装成为波导模块。小信号测试结果表明：该功放芯片工作频率为125~150 GHz, 最高增益在131 GHz为21 dB, 最低增益在150 GHz为17 dB, 通带内S22小于-7 dB, S11小于-10 dB。大信号测试结果表明：该功放模块在128~146 GHz带内输出功率都大于13 dBm, 在139 GHz时, 具有最高输出功率为13.6 dBm, 且1 dB压缩功率为12.9 dBm。     

A super junction SiGe low-loss fast switching power diode

This paper proposes a novel super junction (SJ) SiGe switching power diode which has a columnar structure of alternating p^- and n^- doped pillar substituting conventional n^- base region and has far thinner strained SiGe p⁺ layer to overcome the drawbacks of existing Si switching power diode. The SJ SiGe diode can achieve low specific on-resistance, high breakdown voltages and fast switching speed. The results indicate that the forward voltage drop of SJ SiGe diode is much lower than that of conventional Si power diode when the operating current densities do not exceed 1000 A/cm², which is very good for getting lower operating loss. The forward voltage drop of the Si diode is 0.66V whereas that of the SJ SiGe diode is only 0.52 V at operating current density of 10 A/cm². The breakdown voltages are 203 V for the former and 235 V for the latter. Compared with the conventional Si power diode, the reverse recovery time of SJ SiGe diode with 20 per cent Ge content is shortened by above a half and the peak reverse current is reduced by over 15%. The SJ SiGe diode can remarkably improve the characteristics of power diode by combining the merits of both SJ structure and SiGe material.