一种用硬件实现的Bayer格式图像恢复算法

针对传统的双线性Bayer彩色图像恢复算法恢复效果不理想,边界部分不明显,局部图像有团块等问题,提出了一种基于硬件实现的Bayer图像快速插值算法。采用梯度算法对Bayer格式图像绿色通道进行恢复,根据像素点所属的颜色组对蓝色通道进行恢复。实验结果表明,本文算法比双线性法有更好的峰值信噪比(PSNR)值,RGB 3个通道的PSNR值均比双线性法高5 dB以上,而且算法消耗时间比双线性法少,恢复的图像视觉效果更好。实验处理一幅512×512的全彩图像仅需要9.3 ms,完全可以满足实时性的要求,因此,本文算法在对实时性要求高的场合有很好的应用前景。     

Gate-controlled low-bias rectifying behaviors in BDC60 molecule

Using first-principles density functional theory and non-equilibrium Greenʼs function formalism for quantum transport calculation, we have investigated the effect of gate voltage on the electronic transport properties of BDC60-based molecular junction. The results show that the transport properties are strongly modulated by the applied gate voltage, and the current–voltage curve displays an obvious rectifying behavior at much low bias region. The mechanism for the rectifying behavior is analyzed by the bias-dependent transmission spectrum, projected density of states, spatial distribution of molecular projected self-consistent Hamiltonian orbitals and voltage drop over the junction.     

基于FPGA的脉冲电源及其控制系统设计

针对等离子体特定领域的应用需求,研制了一种基于上位机监控且具有手动/自动控制功能的脉冲电源。详细介绍了脉冲电源主电路、检测电路、驱动电路、数字脉宽调制（DPWM）产生模块以及脉冲变压器的设计方法。该电源采用现场可编程门阵列（FPGA）作为主控芯片,产生DPWM信号及继电器控制信号,经驱动电路放大后驱动逆变全桥及继电器。设计了过温和短路保护电路,通过DS18B20温度传感器和QBC10PS5霍尔电流传感器对电源模块的工作温度和电流进行实时采样。实际应用测试表明,该电源满足设计指标要求。     

New Design for Quantum Dots Cellular Automata to obtain Fault Tolerant Logic Gates

In this paper, we analyze fault tolerance properties of the Majority Gate, as the main logic gate for implementation with Quantum dots Cellular Automata (QCA), in terms of fabrication defect. Our results demonstrate the poor fault tolerance properties of the conventional design of Majority Gate and thus the difficulty in its practical application. We propose a new approach to the design of QCA-based Majority Gate by considering two-dimensional arrays of QCA cells rather than a single cell for the design of such a gate. We analyze fault tolerance properties of such Block Majority Gates in terms of inputs misalignment and irregularity and defect (missing cells) in assembly of the array. We present simulation results based on semiconductor implementation of QCA with an intermediate dimensional dot of about 5 nm in size as opposed to magnetic dots of greater than 100 nm or molecular dots of 2–5Å. Our results clearly demonstrate the superior fault tolerance properties of the Block Majority Gate and its greater potential for a practical realization. We also show the possibility of designing fault tolerant QCA circuits by using Block Majority Gates.     

Reducing cross-flow vibrations of underflow gates: Experiments and numerical studies

An experimental study is combined with numerical modelling to investigate new ways to reduce cross-flow vibrations of hydraulic gates with underflow. A rectangular gate section placed in a flume was given freedom to vibrate in the vertical direction. Horizontal slots in the gate bottom enabled leakage flow through the gate to enter the area directly under the gate which is known to play a key role in most excitation mechanisms.For submerged discharge conditions with small gate openings the vertical dynamic support force was measured in the reduced velocity range 1.5<V_r<10.5 for a gate with and without ventilation slots. The leakage flow significantly reduced vibrations. This attenuation was most profound in the high stiffness region at 2<V_r<3.5.Two-dimensional numerical simulations were performed with the Finite Element Method to assess local velocities and pressures for both gate types. A moving mesh covering both solid and fluid domain allowed free gate movement and two-way fluid–structure interactions. Modelling assumptions and observed numerical effects are discussed and quantified. The simulated added mass in still water is shown to be close to experimental values. The spring stiffness and mass factor were varied to achieve similar response frequencies at the same dry natural frequencies as in the experiment. Although it was not possible to reproduce the vibrations dominated by impinging leading edge vortices (ILEV) at relatively low V_r, the simulations at high V_r showed strong vibrations with movement-induced excitation (MIE). For the latter case, the simulated response reduction of the ventilated gate agrees with the experimental results. The numerical modelling results suggest that the leakage flow diminishes pressure fluctuations close to the trailing edge associated with entrainment from the wake into the recirculation zone directly under the gate that most likely cause the growing oscillations of the ordinary rectangular gate.     

基于现场可编程门阵列的通用化PCM编码器

针对目前弹载遥测系统对PCM编码器提出的通用化应用需求,提出了一种基于现场可编程门阵列的通用化PCM编码器。该方法以软件为主的信号处理方式代替硬件处理,采用Verilog HDL语言和模块化的设计思想将编码器的各功能模块集成在单片FPGA中,通过功能模块的积木式组合和参数配置实现了对被测弹箭系统的采集编码。仿真测试结果表明该编码器满足绝大多数弹箭遥测系统的参数测试要求,在弹箭遥测系统中飞行试验结果表明该编码器在全弹道飞行过程中工作稳定可靠,该编码器实现了通用化的要求。     

A novel lateral diffused metal oxide semiconductor (LDMOS) by attracting the electric field Lines

In this paper, a novel silicon on insulator (SOI) lateral diffused metal oxide semiconductor (LDMOS) transistor with high voltage and high frequency performance is presented. In this work we try to reduce the electric field crowding in the drift region. The proposed structure consists of a metal in the buried oxide and also connected to the source. The inserted metal attracts the electric field lines in the buried oxide. It causes 67% improvement in the breakdown voltage in comparison with a conventional SOI-LDMOS (C-LDMOS). Our simulations with two dimensional ATLAS simulator show that the gate-drain capacitance improves in the proposed structure. The unilateral power gain also enhances. So, the proposed structure is suitable for high voltage and high frequency applications.     

Impact of post-nitridation annealing on ultra-thin gate oxide performance

Decoupled-Plasma Nitridation (DPN) process with high level of nitrogen incorporation is widely used in the state-of-the-art technology, in order to reduce gate leakage current and boron penetration. However, due to the low temperature DPN process, the post-nitridation annealing treatment is required to improve the ultra-thin gate oxide integrity. In this paper, the effect of post-nitridation annealing on DPN ultra-thin gate oxide was investigated. The device performance and reliability were evaluated in three different post-nitridation annealing ambient (N₂/O₂, He, and NO).     

TEOS-based low-pressure chemical vapor deposition for gate oxides in 4H–SiC MOSFETs using nitric oxide post-deposition annealing

The use of SiO₂/4H–SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) can be problematic due to high interface state density (D_it) and low field-effect mobility (μ_fe). Here, we present a tetra-ethyl-ortho-silicate (TEOS)-based low-pressure chemical vapor deposition (LPCVD) method for fabricating the gate oxide of 4H–SiC MOSFETs using nitric oxide post-deposition annealing. SiO₂/4H–SiC MOS capacitors and MOSFETs were fabricated using conventional wet and TEOS oxides. The measured effective oxide charge density (Q_eff) and D_it of the TEOS-based LPCVD SiO₂/4H–SiC MOS capacitor with nitridation were 4.27 × 10¹¹ cm⁻² and 2.99 × 10¹¹ cm⁻²eV⁻¹, respectively. We propose that the oxide breakdown field and barrier height were dependent on the effective Q_eff. The measured μ_fe values of the SiO₂/4H–SiC MOSFETs with wet and TEOS oxides after nitridation were, respectively, 11.0 and 17.8 cm²/V due to the stable nitrided interface between SiO₂ and 4H–SiC. The proposed gate stack is suitable for 4H–SiC power MOSFETs.     

基于门控制电催化效应的分子印迹传感器

以绿麦隆为模板分子,在镍电极表面聚合制得绿麦隆分子印迹膜。洗脱后的分子印迹膜重新吸附不同浓度绿麦隆分子,在印迹膜上形成不同量的印迹孔穴,H2O2通过印迹孔穴在镍电极表面产生电催化氧化,从而形成门控制电催化效应,以此对绿麦隆进行定量分析。研究表明,镍电极对H2O2有较好的催化效果,分子印迹聚合膜中模板分子、功能单体和交联剂的摩尔配比为1∶12∶30,重吸附时间为10 min,测试缓冲液pH=7.2。H2O2的催化电流值与绿麦隆浓度在1.0×10-4～4.0×10-7 mol/L范围内呈良好的线性关系;检出限为2.9×10-8 mol/L。将传感器应用于农田水样的检测,其回收率在97%～103%之间。