Scheme for teleporting an unknown atomic state to any node in a quantum communication network

We propose a scheme for teleporting an unknown atomic state. In order to realize the teleportation to any node in a quantum communication network, an n-atom Greenberger-Horne-Zeilinger (GHZ) state is needed, which is utilized as the quantum channel. From this n-atom GHZ state, two-node entanglement of processing and receiving teleported states can be obtained through the quantum logic gate manipulation. Finally, for the unequally weighted GHZ state, probabilistic teleportation is shown.     

Phenomenology of nonlocal cellular automata

Dynamical systems with nonlocal connections have potential applications to economic and biological systems. This paper studies the dynamics of nonlocal cellular automata. In particular, all two-state, three-input nonlocal cellular automata are classified according to the dynamical behavior starting from random initial configurations and random wirings, although it is observed that sometimes a rule can have different dynamical behaviors with different wirings. The nonlocal cellular automata rule space is studied using a mean-field parametrization which is ideal for the situation of random wiring. Nonlocal cellular automata can be considered as computers carrying out computation at the level of each component. Their computational abilities are studied from the point of view of whether they contain many basic logical gates. In particular, I ask the question of whether a three-input cellular automaton rule contains the three fundamental logical gates: two-input rules AND and OR, and one-input rule NOT. A particularly interesting edge-of-chaos nonlocal cellular automaton, the rule 184, is studied in detail. It is a system of coupled selectors or multiplexers. It is also part of the Fredkin's gate—a proposed fundamental gate for conservative computations. This rule exhibits irregular fluctuations of density, large coherent structures, and long transient times.     

非对称Halo异质栅应变Si SOI MOSFET的二维解析模型

为了进一步提高深亚微米SOI (Silicon-On-Insulator) MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) 的电流驱动能力, 抑制短沟道效应和漏致势垒降低效应, 提出了非对称Halo异质栅应变Si SOI MOSFET. 在沟道源端一侧引入高掺杂Halo结构, 栅极由不同功函数的两种材料组成. 考虑新器件结构特点和应变的影响, 修正了平带电压和内建电势. 为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型. 模型详细分析了应变对表面势、表面场强、阈值电压的影响, 考虑了金属栅长度及功函数差变化的影响. 研究结果表明,提出的新器件结构能进一步提高电流驱动能力, 抑制短沟道效应和抑制漏致势垒降低效应, 为新器件物理参数设计提供了重要参考. 关键词： 非对称Halo 异质栅 应变Si 短沟道效应     

异质多晶SiGe栅应变Si NMOSFET物理模型研究

结合了“栅极工程”和“应变工程”二者的优点, 异质多晶SiGe栅应变Si MOSFET, 通过沿沟道方向使用不同功函数的多晶SiGe材料, 在应变的基础上进一步提高了MOSFET的性能. 本文结合其结构模型, 以应变Si NMOSFET为例, 建立了强反型时的准二维表面势模型, 并进一步获得了其阈值电压模型以及沟道电流的物理模型. 应用MATLAB对该器件模型进行了分析, 讨论了异质多晶SiGe栅功函数及栅长度、衬底SiGe中Ge组分等参数对器件阈值电压、沟道电流的影响, 获得了最优化的异质栅结构. 模型所得结果与仿真结果及相关文献给出的结论一致, 证明了该模型的正确性. 该研究为异质多晶SiGe栅应变Si MOSFET的设计制造提供了有价值的参考. 关键词： 异质多晶SiGe栅 应变Si NMOSFET 表面势 沟道电流     

一个次氯酸根比色荧光探针及其逻辑行为（英文）

利用次氯酸根(ClO-)的氧化性质和Cu+与Cu2+不同的配位性质,一种高效的可用于探测ClO-的铜离子化合物CS1被合成出来。通过吸收和发射光谱系统地研究了CS1对ClO-的传感性能。结果表明,在Cu+存在条件下,CS1的光谱强烈受到OCl-影响:最大吸收峰从396 nm红移到545 nm(Δλ=149 nm);520nm处的荧光强度降低近25倍。以Cu+和ClO-为输入信号,以470 nm和396 nm吸收峰比值(A470/A396)为输出信号,构建了一个基于CS1的AND逻辑门,并且可以用乙二胺四乙酸二钠盐(EDTA)对其进行简单重置。     

Interfacial characteristics of Al/Al2O3/ZnO/n-GaAs MOS capacitor

The interfacial characteristics of Al/Al2O3/ZnO/n-GaAs metal-oxide-semiconductor (MOS) capacitor are investigated. The results measured by X-ray photoelectron spectroscopy (XPS) and high-resolution transmission electron microscopy (HRTEM) show that the presence of ZnO can effectively suppress the formations of oxides at the interface between the GaAs and gate dielectric and gain smooth interface. The ZnO-passivated GaAs MOS capacitor exhibits a very small hysteresis and frequency dispersion. Using the Terman method, the interface trap density is extracted from C-V curves. It is found that the ZnO layer can effectively improve the interface quality.     

Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

TOT measurement implemented in FPGA TDC

Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays(FPGAs), FPGA time-to-digital converters(TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold(TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method,TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.     

二维光子晶体全光异或门的设计及研究

分析了二维光子晶体马赫-曾德尔干涉仪的传输特性,将二维光子晶体波导、环形腔和马赫-曾德尔干涉仪有效结合,提出了一种基于二维光子晶体马赫-曾德尔干涉仪的异或门设计。用平面波展开法分析二维光子晶体能带结构,并用时域有限差分法验证光信号在该器件中的电场稳态分布。结果表明,该结构能够实现异或逻辑,且具有高逻辑对比度7.88 dB,快速响应周期0.388 ps和高传输速率7.87 Tbit/s;并且该器件结构尺寸仅为13 μm×14 μm,易于集成。该异或逻辑结构中引入了二维光子晶体马赫-曾德尔干涉仪,使得光子晶体逻辑门结构的设计更加多样,并为二维光子晶体半加器与全加器的设计提供了基础,具有重要的研究意义。     

All-optical logic AND-NOR gate with three inputs based on cross-gain modulation in a semiconductor optical amplifier

We report the realization of a novel all-optical logic AND-NOR gate based on cross-gain modulation (XGM). The used scheme requires only one SOA to perform the logic gate with three input signals. A 8.5 dB dynamic extinction ratio with a switching time of about 650 ps for the rise time and 100 ps for the fall time.