激光对分子振动态的控制与量子Fredkin逻辑门

基于激光相干合成分子的局域模振动态,提出利用激光对分子振动态的控制实现量子Fredkin逻辑门的功能,并对方案的特点及可行性进行分析.     

Mixed noise removal algorithm of EBAPS image under low illumination condition based on FPGA北大核心CSCD

In order to solve the problem that single median filtering and gaussian filtering algorithm is not effective in suppressing impulse noise and poisson noise simultaneously in low illumination image, and the edge detail protection is insufficient, an open and close mix-median-gaussian (OCMMG) filtering algorithm based on field programmable gate array (FPGA) was proposed. Firstly, the minimum four-direction difference was used to detect the anomaly degree of each pixel point, the weight was allocated according to the threshold of pulse noise discrimination, and the first step was filtering. Then, the four-direction edge detection algorithm was used to extract image edges, and the second step was filtered according to the set edge confidence characterization value. Finally, the images collected by electron bombarded active pixel sensor (EBAPS) under the condition of 1×10−3 lx illumination were processed by FPGA in real time. The experimental results show that the FPGA processing results are consistent with the software simulation processing results. Compared with the median filtering and gaussian filtering algorithm, the peak signal-to-noise ratio (PSNR) of the algorithm is improved by 3.23% and 16.34%, the structural similarity is improved by 14.66% and 33.86%, and the edge retention index is improved by 0.49% and 4.21%, respectively, which can effectively remove the mixed noise of EBAPS image and meet the real-time requirements. © 2022 Editorial office of Journal of Applied Optics. All rights reserved.     

基于线计算的全加器设计

随着集成电路特征尺寸的不断缩小, 互连线在芯片内部占的比重越来越大, 但是互连线仅用于数据传输, 芯片计算能力仍然需要依靠晶体管开关实现. 如何在有限的硬件资源内进一步提高芯片的计算能力, 已经成为当前集成电路设计的核心问题. 本文通过研究金属互连线间电容耦合效应, 采用互连线串扰现象完成逻辑运算的思想, 提出一种基于线计算的全加器设计方案. 该方案首先建立线计算模型, 通过调整反相器阈值和不同干扰线与受扰线之间电容耦合强度匹配技术, 采用相同线计算电路结构实现不同功能的逻辑门电路; 然后, 在逻辑门的基础上实现基于线计算的全加器; 最后, 在TSMC 65nm CMOS工艺下仿真验证. 结果表明, 所设计的线计算电路具有正确逻辑功能, 与传统设计方法相比, 线计算逻辑门具有更低开销, 且线计算电路具有抗逆向工程能力.     

基于RTD可编程逻辑门的n变量函数实现算法

共振隧穿二极管（RTD）可编程逻辑门是一种由单双稳态转换逻辑单元（MOBILE）及正、负输入分支组成的阈值逻辑电路。基于二进制神经元模型中的三层网络结构,提出了基于RTD可编程逻辑门的n变量函数实现算法。按照汉明距离由大到小的顺序,搜索最优输入向量,用定理1或定理2方法产生隐层函数,通过变换次数,确定输入向量的真假及隐层函数的权重。由于定义了最优输入向量及变换次数,提高了算法的准确性;又由于采用了定理2方法,令设计的电路更简单。     

Note on Generalized Quantum Gates and Quantum Operations

Recently, Gudder proved that the set of all generalized quantum gates coincides the set of all contractions in a finite-dimensional Hilbert space (S. Gudder, Int. J. Theor. Phys. 47:268–279, 2008). In this note, we proved that the set of all generalized quantum gates is a proper subset of the set of all contractions on an infinite dimensional separable Hilbert space ℋ. Meanwhile, we proved that the quantum operation deduced by an isometry is an extreme point of the set of all quantum operations on ℋ. This subject is supported by NSF of China (10571113).     

Bioinspired Nanozymes with pH‐Independent and Metal Ions‐Controllable Activity: Field‐Programmable Logic Conversion of Sole Logic Gate System

In nature, different environmental factors make organisms to be programmed into different forms. However, it is difficult and significant to realize the field‐programmable logic conversion of sole logic system for molecular logic gates. Here, the concept of pH‐programmable “logic conversion” on the single logic gate based on the peculiar enzyme‐mimicking activity is presented. Inspired by natural enzymes with high pH‐stability and metal ions‐stimulated activity, pH‐independent and metal ions‐controllable catalase mimics (Co₃O₄ nanozymes) are designed by protein‐directed method. Although pH cannot directly change the activity of nanozymes, pH can change the existence state of metal ions and then the electron transfer rate on nanozymes. So, versatile roles of metal ions for catalase‐like and electrocatalytic activities are discovered on the premise of pH‐independency. For the proof‐of‐concept, OR/INHIBIT‐ and INHIBIT/AND‐switchable logic gates are facilely constructed using pH as the environmental stimulus and metal ions as inputs. Hence, the transformation of logic gate functions is realized without the change of logic gate elements and input molecules. This contribution may not only broaden the species and application area of nanozymes, but also open novel avenues for the molecular logic conversion and the metal ions sensor.     

脉冲功率应用的IGBT快速驱动电路

根据绝缘栅双极型晶体管(IGBT)的工作特性,研究设计了一种应用于脉冲功率系统的开关驱动电路,实现了IGBT的快速开通。阐述了驱动电路的原理,设计了基于平面变压器的驱动电路,在驱动芯片基础上为栅极提供幅值为60 V脉冲电压,提高开关速度。最后使用Blumlein双线结构对驱动电路的性能进行了实验验证。应用这种驱动方式,提高了集电极电流上升速率。实验结果表明,在1000 V的工作电压下,通过IGBT的脉冲电流达到了470.53 A,脉冲前沿为40 ns,di/dt达到9.41 A/ns,相比数据手册提供的数据,该电流上升速度提高了7.53倍,实现了对IGBT的快速驱动。     

铟镓锌氧薄膜晶体管的悬浮栅效应研究

为了避免光照对铟镓锌氧薄膜晶体管(InGaZnO thin film transistors,IGZO TFTs)电学特性的影响,IGZO TFT要增加遮光金属层.本文研究了遮光金属栅极悬浮时,IGZO TFT的输出特性.采用器件数值计算工具TCAD(technology computer-aided design)分析了IGZO层与栅介质层界面处电势分布,证实了悬浮栅(floating gate,FG)IGZO TFT输出曲线的不饱和现象是由悬浮栅与TFT漏端的电容耦合造成.基于等效电容的电压分配方法,提出了悬浮栅IGZO TFT电流的一阶模型.TCAD数值分析及一阶物理模型结果与测试具有较高程度的符合,较完整地解释了悬浮栅IGZO TFT的电学特性.     

Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

TOT measurement implemented in FPGA TDC

Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays(FPGAs), FPGA time-to-digital converters(TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold(TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method,TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.