A novel sensitivity model for short nets

For modern processes at deep sub-micron technology nodes, yield design, especially the design at the layout stage is an important way to deal with the problem of manufacturability and yield. In order to reduce the yield loss caused by redundancy material defects, the choice of nets to be optimized at first is an important step in the process of layout optimization. This paper provides a new sensitivity model for a short net, which is net-based and reflects the size of the critical area between a single net and the nets around it. Since this model is based on a single net and includes the information of the surrounding nets, the critical area between the single net and surrounding nets can be reduced at the same time. In this way, the efficiency of layout optimization becomes higher. According to experimental observations, this sensitivity model can be used to choose the position for optimization. Compared with the chip-area-based and basic- layout-based sensitivity models, our sensitivity model not only has higher efficiency, but also confirms that choosing the net to be optimized at first improves the design.     

An adaptive heuristic algorithm for VLSI test vectors selection

The increasing complexity of today’s system-on-a-chip designs is putting more pressure on the already stressed design verification process. The verification plan must cover several individual cores as well as the overall chip design. Conditions to be verified are identified by the system’s architects, the designers, and the verification team. Testing for these conditions is a must for the design to tape out, especially for high priority conditions. A significant bottleneck in the verification process of such designs is that not enough time is usually given to the final coverage phase, which makes computing cycles very precious. Thus, intelligent selection of test vectors that achieve the best coverage using the minimum number of computing cycles is crucial for on time tape out. This paper presents a novel heuristic algorithm for test vectors selection. The algorithm attempts to achieve the best coverage level while minimizing the required number of computing cycles.     

编码系统研究及VLSI实现

提出了一种JPEG2000编码系统结构和VLSI方案.该方案以小波子带为单位,多套并行处理.对JPEG2000标准中各个模块的算法进行了逻辑化简、并行编码等优化.如采用双行并行9/7提升小波分解,条带并行的比特平面编码,简化区间更新和并行归一化算术编码等.各模块均以流水线方式工作,其中的比特平面编码和算术编码采用异步流水线方式动态分配执行时间,加速比均接近于流水段数3.以图像信号产生板送入原始图像,编码后送入PC机进行码流截断和解压缩.该系统在各个压缩率下的信噪比与LuraWave商用压缩软件的差距均在0.8 dB之内,可见改进后的算法可行且有效,像元时钟可达20 MHz.     

一种基于色度学的RGBW信号映射算法评价方法

随着对高亮度、低功耗绿色显示技术的不断追求,RGBW显示技术成为了国内外的热门研究方向,已有多种RGBW显示器在市场上开始推广。由于将传统显示器rgb信号转换到RGBW显示器RGBW信号的映射算法不仅需要保留初始颜色,且需要兼容具有不同子像素布局方式的RGBW显示器,因此,信号映射算法成为RGBW显示的关键。在介绍现有的五种信号映射算法的基础上,分析了RGBW显示器中新增的白色子像素对显示颜色的作用方式以及现有四种RGBW子像素布局方式对映射算法显示效果的影响;提出了优秀映射算法应满足的三点要求,并据此推导出优秀映射算法的普适性等式及衡量映射算法亮度提升能力的亮度因子;针对五种映射算法的模拟实验表明：满足普适性等式的映射算法能更好地保留初始颜色的色调和饱和度,亮度因子可有效表征算法对亮度的提升能力。该模型不仅可用于评价现有映射算法,而且可为新型映射算法的研究提供理论指导,使之兼容于具有不同硬件参数和子像素布局的显示器,有助于RGBW显示技术的普及推广。     

Marx调制器单元设计和叠加测试

 基于单元器件的成功研制,介绍了Marx调制器单元充放电回路、电压和电流的实时监测以及控制系统和连锁保护等功能的设计和实现。对IGBT固态开关的静态、动态均压进行分析和模拟,采用RCD缓冲电路实现IGBT的动态均压;对控制系统改进和优化,设计了专用电源转换模块;分压电路和电流霍尔采样回路分别实现调制器单元电压和电流的检测;连锁保护功能由控制系统和继电器控制完成。所有部件按照电气标准设计在调制器单元支架上。经过测试的4个单元进行了叠加试验,4个单元总输出24 kV,各器件在高压试验中工作正常。     

FLPS-工厂平面布置系统

本文在微机上根据物流系统分析法规定的程式设计了工厂平面布置系统,该系统能按规定打印各阶段所需要的工作表格;采用受控分支搜索的相关平面布置法和人机交互修正法相结合,输出多个优化的布置方案;并用评价体系对各个优化方案进行综合评估.设计结果既能直观地在显示器上显示,又能在绘图仪上绘出.     

Symmetrizing a Hessenberg matrix: Designs for VLSI parallel processor arrays

A symmetrizer of a nonsymmetric matrix A is the symmetric matrixX that satisfies the equationXA =A ^tX, wheret indicates the transpose. A symmetrizer is useful in converting a nonsymmetric eigenvalue problem into a symmetric one which is relatively easy to solve and finds applications in stability problems in control theory and in the study of general matrices. Three designs based on VLSI parallel processor arrays are presented to compute a symmetrizer of a lower Hessenberg matrix. Their scope is discussed. The first one is the Leiserson systolic design while the remaining two, viz., the double pipe design and the fitted diagonal design are the derived versions of the first design with improved performance.     

Guided Local Search for Final Placement in VLSI Design

The design of a VLSI circuit consists of two main parts: First, the logical functionality of the circuit is described, and then the physical layout of the modules and connections is settled. In the latter process one wishes to place the modules such that the necessary wiring becomes as small as possible in order to minimize area usage and delays on signal paths. The placement problem is the subproblem of the layout problem which considers the geometric locations of the modules. A new heuristic is presented for the general cell placement problem where the objective is to minimize total bounding box netlength. The heuristic is based on the Guided Local Search (GLS) metaheuristic. GLS modifies the objective function in a constructive way to escape local minima. Previous attempts to use local search on final (or detailed) placement problems have often failed as the neighbourhood quickly becomes too excessive for large circuits. Nevertheless, by combining GLS with Fast Local Search it is possible to focus the search on appropriate sub-neighbourhoods, thus reducing the time complexity considerably. Comprehensive computational experiments with the developed algorithm are reported on a broad range of industrial circuits. The experiments demonstrate that the developed algorithm is able to improve the estimated routing length of large-sized layouts with as much as 20 percent when compared to existing algorithms.     

基于圆形件排样问题的遗传算法研究

排样性问题是一类优化求解问题,在遗传算法求解过程中,若所用的算法是不收敛的,则无法得到最优解.给出了一种混合式遗传算法,并证明了算法是完全收敛的,能够得到全局最优解.     

VLSI Circuit Performance Optimization by Geometric Programming

Delay of VLSI circuit components can be controlled by varying their sizes. In other words, performance of VLSI circuits can be optimized by changing the sizes of the circuit components. In this paper, we define a special type of geometric program called unary geometric program. We show that under the Elmore delay model, several commonly used formulations of the circuit component sizing problem considering delay, chip area and power dissipation can be reduced to unary geometric programs. We present a greedy algorithm to solve unary geometric programs optimally and efficiently. When applied to VLSI circuit component sizing, we prove that the runtime of the greedy algorithm is linear to the number of components in the circuit. In practice, we demonstrate that our unary-geometric-program based approach for circuit sizing is hundreds of times or more faster than other approaches.