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41.
组合刻蚀法制备窄带滤光片列阵 总被引:4,自引:0,他引:4
介绍了组合刻蚀法制备窄带滤光片列阵的基本原理和制备工艺,这是一种效率非常高的制备方法,只需N次刻蚀就可以完成2N通道窄带滤光片列阵的制备,而且可以用于制备不同波段窄带滤光片列阵。展示了可见-近红外波段32通道窄带滤光片列阵和中红外波段16通道窄带滤光片列阵的实验结果,其中32通道窄带滤光片列阵的带通峰位基本呈线性分布在774.7~814.2 nm之间,所有滤光片的半峰全宽都非常窄(δλ<1.5 nm),相应于δλ/λ<0.2%,半峰全宽最窄的滤光片达到0.8 nm,相应于δλ/λ<0.1%,其带通峰位λ=794.3 nm;各通道的带通透过率在21.2%~32.4%之间,大部分在30%左右。 相似文献
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We present an arrayed waveguide grating multi-wavelength laser (MWL). The device is operated with five wave- length channels of 194 GHz spacing around a central wavelength of 1.57μm. A side mode suppression ratio of better than 35 dB for all channels is demonstrated. A very attractive feature of the MWL is that it has been realized by a novel one step regrowth approach to achieve a high quality active and passive interface. 相似文献
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Surface photovoltage spectroscopy equations for cathode materials with an AlxGa1-x As buffer layer are determined in order to effectively measure the body parameters for transmission-mode (t-mode) photocathode materials before Cs-O activation.Body parameters of cathode materials are well fitted through experiments and fitting calculations for the designed AlxGa1-x As/GaAs structure material.This investigation examines photo-excited performance and measurements of body parameters for t-mode cathode materials of different doping structures.It also helps study various doping structures and optimize structure designs in the future. 相似文献
45.
Wafer-Level Testable High-Speed Silicon Microring Modulator Integrated with Grating Couplers
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A wafer-level testable silicon-on-insulator-based microring modulator is demonstrated with high modulation speed, to which the grating couplers are integrated as the fiber-to-chip interfaces. Cost-efflcient fabrications are realized with the help of optical structure and etching depth designs. Grating couplers and waveguides are patterned and etched together with the same slab thickness. Finally we obtain a 3-dB coupling bandwidth of about 6Ohm and 10 Gb/s nonreturn-to-zero modulation by wafer-level optical and electrical measurements. 相似文献
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A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is proposed to enhance the image quality. The system can also process fixed patten noise (FPN) reduction, color correction, gamma correction, RGB/YUV space transfer, etc. The chip is controlled by sensor regis- ters by inter-integrated circuit (I2C) interface. The voltage for both the front-end analog and the pad cir- cuits is 2.8 V, and the volatge for the image signal processing is 1.8 V. The chip running under the external 13.5-MHz clock has a video data rate of 30 frames/s and the measured power dissipation is about 75 roW. 相似文献
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