全文获取类型
收费全文 | 1125篇 |
免费 | 37篇 |
国内免费 | 32篇 |
专业分类
化学 | 577篇 |
晶体学 | 1篇 |
力学 | 6篇 |
综合类 | 4篇 |
数学 | 16篇 |
物理学 | 154篇 |
无线电 | 436篇 |
出版年
2024年 | 1篇 |
2023年 | 6篇 |
2022年 | 9篇 |
2021年 | 20篇 |
2020年 | 18篇 |
2019年 | 8篇 |
2018年 | 15篇 |
2017年 | 7篇 |
2016年 | 41篇 |
2015年 | 34篇 |
2014年 | 66篇 |
2013年 | 43篇 |
2012年 | 157篇 |
2011年 | 113篇 |
2010年 | 116篇 |
2009年 | 110篇 |
2008年 | 81篇 |
2007年 | 54篇 |
2006年 | 57篇 |
2005年 | 57篇 |
2004年 | 51篇 |
2003年 | 55篇 |
2002年 | 13篇 |
2001年 | 18篇 |
2000年 | 8篇 |
1999年 | 9篇 |
1998年 | 2篇 |
1996年 | 7篇 |
1995年 | 5篇 |
1994年 | 4篇 |
1993年 | 2篇 |
1992年 | 5篇 |
1989年 | 1篇 |
1983年 | 1篇 |
排序方式: 共有1194条查询结果,搜索用时 875 毫秒
91.
92.
Jonathan R. Haigh Author Vitae Lawrence T. Clark Author Vitae 《Integration, the VLSI Journal》2008,41(4):509-523
A fast low power four-way set-associative translation lookaside buffer (TLB) is proposed. The proposed TLB allows single clock phase accesses at clock frequencies above 1 GHz. Comparisons to a conventional fully associative CAM tagged TLB, which is the type most commonly used in embedded processors, with the same number of entries on a 65 nm low standby power process show that the proposed design has 28% lower delay and up to 50% lower energy delay product. Unlike previous set-associative TLBs, which replicate the TLB to support multiple page sizes, multiple page sizes are supported on a way-by-way basis. Alternative conventional CAM tagged and set-associative TLBs are investigated with regard to access latency, power dissipation and hit rates. 相似文献
93.
Jaime Ramírez-Angulo Author Vitae Author Vitae Antonio Lopez-Martin Author Vitae Author Vitae 《Integration, the VLSI Journal》2008,41(4):539-543
A simple dynamic biasing scheme to extend the input/output range of cascode amplifiers is introduced. It requires minimum extra hardware and no additional power consumption. A dynamic biased telescopic op-amp is discussed as an application example. Experimental results of a fabricated test chip in 0.5 μm CMOS technology are presented that verify the proposed technique. 相似文献
94.
95.
96.
Dahmani Mohammed Keche MokhtarAuthor VitaeOuamri AbdelazizAuthor Vitae Meche AbdelkrimAuthor Vitae 《AEUE-International Journal of Electronics and Communications》2010,64(12):1123-1127
In this paper we present an new approach based on two filters αβ and αβγ using Interacting Multiples Models (IMM) design instead of a Kalman filter second and third order for the tracking a single maneuver target. The comparison between the proposed filter and the IMM improves the computing time amount about 60% while having a high accuracy. 相似文献
97.
Huanlai XingAuthor Vitae Yuefeng JiLin BaiAuthor Vitae Yongmei SunAuthor Vitae 《AEUE-International Journal of Electronics and Communications》2010,64(12):1105-1113
This paper investigates how to minimize the required coding resources in network-coding-based multicast scenarios. An evolutionary algorithm (MEQEA) is proposed to address the above problem. Based on quantum-inspired evolutionary algorithm (QEA), MEQEA introduces multi-granularity evolution mechanism which allows different chromosomes, at each generation, to have different rotation angle step values for update. In virtue of this mechanism, MEQEA significantly improves its capability of exploration and exploitation, since its optimization performance is no longer overly dependant upon the single rotation angle step scheme shared by all chromosomes. MEQEA also presents an adaptive quantum mutation operation which is able to prevent local search efficiently. Simulations are carried out over a number of network topologies. The results show that MEQEA outperforms other heuristic algorithms and is characterized by high success ratio, fast convergence, and excellent global-search capability. 相似文献
98.
Vamsi Krishna Velidi Subrata SanyalAuthor Vitae 《AEUE-International Journal of Electronics and Communications》2010,64(12):1173-1177
A simple design of a sharp-rejection microstrip bandpass (BPF) filter is presented. By creating multiple transmission zeros in the lower and upper stopbands, sharp rejection characteristics are obtained. The basic filter unit consists of a single parallel coupled-line section and an open-ended stub. A lossless transmission line model approach is used to derive the design equations for frequency responses and transmission zero positions. The bandwidths are controllable by the zero locations that in turn are controlled by varying the impedances of the configuration. To validate theoretical predictions, two prototype BPFs operating at lower band 2.4 GHz of WLAN are fabricated in microstrip form. 相似文献
99.
Montree Kumngern Boonying KnobnobAuthor VitaeKobchai DejhanAuthor Vitae 《AEUE-International Journal of Electronics and Communications》2010,64(10):934-939
This paper describes a new electronically tunable three inputs and single output voltage-mode universal biquadratic filter based on simple CMOS operational transconductance amplifiers (OTAs) and grounded capacitors. The proposed configuration provides lowpass, highpass, bandpass, bandstop and allpass voltage responses at a high impedance input terminal, which enable easy cascadability. Additionally, the circuit parameters ωo and Q can be set orthogonally by adjusting the transconductances and grounded capacitors. The filter also offers an independent electronic control of parameters ωo by adjusting the transconductance through the bias current/voltage of the OTA. For realizing all the filter responses, no critical component matching condition is required, and all the incremental parameter sensitivities are low. PSPICE simulation results are performed to confirm the theoretical analysis. 相似文献
100.
Amir Kaivani Author Vitae 《Integration, the VLSI Journal》2010,43(1):34-41
Decimal computer arithmetic is experiencing a revived popularity, and there is quest for high-performance decimal hardware units. Successful experiences on binary computer arithmetic may find grounds in decimal arithmetic. For example, the traditional fully redundant (i.e., the result and both of the operands are represented in a redundant format) and semi-redundant (i.e., the result and only one of the operands are redundant) binary addition schemes have influenced the design and implementation of similar decimal arithmetic units. However, special comparison and correction steps are required when decimal arithmetic algorithms are implemented on binary hardware. To circumvent these difficulties, alternative encodings of decimal digits and a variety of decimal arithmetic algorithms have been examined by many researchers over decades. In this paper we offer a new redundant decimal digit set [−8, 9] and a fully redundant addition/subtraction scheme. The proposed digit set, faithfully encoded as a mix of posibits, negabits, and unibits, is shown to obviate the need for any compare-to-9 operations and leads to minimal penalty subtraction using the addition circuitry. Moreover, conversion from the standard BCD encoding to the proposed stored-unibit encoding is possible with the latency of one logic level. However, the reverse conversion, like any other redundant to nonredundant conversion, involves carry propagation. 相似文献