Design metal-dot based QCA circuits using SPICE model

This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulating the basic logic gates such as inverter and majority voter. The proposed model makes it possible to design and simulate QCA combinational circuits and hybrid circuits of QCA and other NANO devices using SPICE. In the second half part of the paper, SET and QCA co-design methodology is proposed and SET is used as a readout interface of the QCA cell array. The SET and QCA hybrid circuit is a promising nano-scale solution.     

A monolithic low-power high-voltage driver for bistable LCDs

A complete low-power high-voltage driver for a 80×104 passive-matrix bistable LCD is integrated in a 0.7 μm CMOS smart-power technology. It features 100 V driving capability on all row and column outputs and comprises all necessary digitally programmable high-voltage generators and multiplexers to synthesize the required complex high-voltage waveforms from a 3 V battery. An original level-shifter design for the high-voltage multiplexers and a dedicated architecture for the programmable high-voltage generators yield an extremely low internal power consumption below 10 mW for the entire driver chip.     

用光电倍增管测量微光像增强器噪声

在微光像增强器成像中,迭加在图像上的时空域噪声,不仅限制系统可工作的最低照度,而且使显示图像有随机蠕动颗粒闪烁的外观。随着低噪声、声增益的光电倍增管的出现,比较精确地测量微弱光信号成为可能,于是在此基础上提出了采用光电倍增管来测试像增强噪声的方法,实验中发现这种方法能比较准确并直观地反映像增强器噪声大小。     

磁脉冲开关在准分子激光器中的应用

本文介绍了用于准分子激光器中的磁脉冲压缩开关的原理和结构，分析了磁脉冲压缩开关在激光器激励电路中的工作过程，并且给出了实验结果。实验表明，磁脉冲庄缩开关有效地压缩电流脉冲宽度，对激励电路中的闸流管起到保护作用。     

Fluorescence detection of pesticides using quantum dot materials – A review

High pesticide use, especially in agriculture, can lead to environmental pollution and potentially adverse health effects. As result, pesticide residues end up in different media, including water and food products, which may serve as direct routes for human exposure. There is thus a continuous drive to develop analytical methods for screening and quantification of these compounds in the different environmental media in which they may occur. Development of quantum dot (QD) based sensors for monitoring pesticides has gained momentum in recent years. QD materials have excellent and unique optical properties and have high fluorescence quantum yields compared to other fluorophores. They have thus been used in numerous studies for the development of probes for organic pollutants. In this paper we specifically review their application as fluorescence probes for pesticide detection in different media including water and in fruits and vegetables. The low detection limits reported demonstrate the potential use of these methods as alternatives to expensive and time-consuming conventional techniques. We also highlight potential limitations that these probes may present when it comes to routine application. Finally we discuss possible future improvements to enhance the selectivity and robustness of these sensors. We note that there is still a need for researchers to develop standardized QD based sensors which could lead to their commercialization and routine application.     

RPB-MD: Providing robust message dissemination for vehicular ad hoc networks

To improve traffic safety and efficiency, it is vital to reliably send traffic-related messages to vehicles in the targeted region in vehicular ad hoc networks (VANETs). In this paper, we propose a novel scheme, relative position based message dissemination (RPB-MD), to reliably and efficiently disseminate messages to the vehicles in the zone-of-relevance. Firstly, the relative position based (RPB) addressing model is proposed to effectively define the intended receivers in the zone-of-relevance. To ensure high message delivery ratio and low delivery delay, directional greedy broadcast routing (DGBR) is introduced to make a group of candidate nodes hold the message for high reliability. Moreover, to guarantee efficiency, the protocol time parameters are designed adaptively according to the message attributes and local vehicular traffic density. The protocol feasibility is analyzed to illustrate the robustness and reliability of RPB-MD. Simulation results show that RPB-MD, compared with representative existing schemes, achieves high delivery ratio, limited overhead, reasonable delay and high network reachability under different vehicular traffic density and data sending rate.     

Modern development methods and tools for embedded reconfigurable systems: A survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.     

Statistical analysis of large on-chip power grid networks by variational reduction scheme

One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches.     

An automated high-level topology generation procedure for continuous-time ΣΔ modulator

This paper presents an automated procedure for generation of high-level topologies for continuous-time ΣΔ modulator system. A functional topology of the system is generated from the given transfer function model of the modulator. Mathematical transformation technique is applied iteratively over the initial topology to generate a functional topology which is optimized for modulator sensitivity, hardware complexity and relative power consumption. This is then implemented using behavioral models of operational transconductance amplifiers and capacitors. The generated high-level topology is ensured to work with reasonable accuracy under non-ideal conditions. The entire procedure has been implemented in Matlab/Simulink environment. Numerical results have been provided to demonstrate the procedure.