Minimax estimation of deterministic parameters in linear models with a random model matrix

We consider the problem of estimating an unknown deterministic parameter vector in a linear model with a random model matrix, with known second-order statistics. We first seek the linear estimator that minimizes the worst-case mean-squared error (MSE) across all parameter vectors whose (possibly weighted) norm is bounded above. We show that the minimax MSE estimator can be found by solving a semidefinite programming problem and develop necessary and sufficient optimality conditions on the minimax MSE estimator. Using these conditions, we derive closed-form expressions for the minimax MSE estimator in some special cases. We then demonstrate, through examples, that the minimax MSE estimator can improve the performance over both a Baysian approach and a least-squares method. We then consider the case in which the norm of the parameter vector is also bounded below. Since the minimax MSE approach cannot account for a nonzero lower bound, we consider, in this case, a minimax regret method in which we seek the estimator that minimizes the worst-case difference between the MSE attainable using a linear estimator that does not know the parameter vector, and the optimal MSE attained using a linear estimator that knows the parameter vector. For analytical tractability, we restrict our attention to the scalar case and develop a closed-form expression for the minimax regret estimator.     

The First Template‐Free Growth of Crystalline Silicon Microtubes

A simple template‐free high‐temperature evaporation method was developed for the growth of crystalline Si microtubes for the first time. As‐grown Si microtubes were characterized using X‐ray diffraction, scanning electron microscopy, transmission electron microscopy, and room‐temperature photoluminescence. The lengths of the Si tubes can reach several hundreds of micrometers; some of them have lengths on the order of millimeters. Each tube has a uniform outer diameter along its entire length, and the typical outer diameter is ≈ 2–3 μm. Most of the tubes have a wall thickness of ≈ 400–500 nm, though a considerable number of them exhibit a very thin wall thickness of ≈ 50 nm. Room‐temperature photoluminescence measurement shows the as‐synthesized Si microtubes have two strong emission peaks centered at ≈ 589 nm and ≈ 617 nm and a weak emission peak centered at ≈ 455 nm. A possible mechanism for the formation of these Si tubes is proposed. We believe that the present discovery of the crystalline Si microtubes will promote further experimental studies on their physical properties and smart applications.     

Low-temperature poly-SiGe alloy growth of high gain/speed pin infrared photosensor with gold-induced lateral crystallization (Au-ILC)

The hydrogenated poly-silicon germanium (poly-SiGe:H) epitaxial film has been investigated using gold-induced lateral crystallization (Au-ILC) technology on a-SiGe:H layers at 10-h 350/spl deg/C annealing temperature and 60-sccm hydrogen (H/sub 2/) content. Using this optimal condition, the growth rate of the induced Au was as large as 15.9 /spl mu/m/h. With a low annealing temperature (/spl les/400/spl deg/C) and large growth rate, this novel technology will be noticeably useful for poly-SiGe:H pin IR-sensing fabrication on a conventional precoated indium tin oxide (ITO)-glass substrate. Under a 1-/spl mu/W IR-LED incident light (with peak wave length at 710 nm) and at a 5-V biased voltage, the poly-SiGe:H pin IR sensor developed by the Au-ILC technology, i.e., an Al (anode)/n poly-SiGe:H/i poly-SiGe:H/p poly-SiGe:H/ITO (cathode)/glass-substrate structure allowed for maximum optical gain and response speed. The optical gains and the response speeds were almost 600 and 130%, respectively, better than that of a traditional pin type. Meanwhile, the FWHM of a poly-SiGe:H pin sensor with Au-ILC technology was reduced from 280 to 150 nm. This reveals excellent IR-sensing selectivity. These IR-sensing trials demonstrated again that the proposed Au-ILC technology has very useful application in the field of low cost integrated circuits on optoelectronic applications.     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.     

High-performance self-aligned SiGeC HBT with selectively grown Si/sub 1-x-y/Ge/sub x/C/sub y/ base by UHV/CVD

Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall, ultrahigh-vacuum chemical vapor deposition, and the effects of incorporating C on the crystallinity of Si/sub 1-x-y/Ge/sub x/C/sub y/ layers and the performance of a self-aligned SiGeC heterojunction bipolar transistor (HBT) were evaluated. A Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was obtained by optimizing the growth conditions. Device performance was significantly improved by incorporating C, as a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned HBT. Fluctuations in device performance were suppressed by alleviating the lattice strain. Furthermore, since the B out diffusion could be suppressed by incorporating C, the cutoff frequency was able to be increased with almost the same base resistance. A maximum oscillation frequency of 174 GHz and an emitter coupled logic gate-delay time of 5.65 ps were obtained at a C content of 0.4%, which shows promise for future ultrahigh-speed communication systems.     

High resistivity measurement of SiC wafers using different techniques

To establish fast, nondestructive, and inexpensive methods for resistivity measurements of SiC wafers, different resistivity-measurement techniques were tested for characterization of semi-insulating SiC wafers, namely, the four-point probe method with removable graphite contacts, the van der Pauw method with annealed metal and diffused contacts, the current-voltage (I-V) technique, and the contactless resistivity-measurement method. Comparison of different techniques is presented. The resistivity values of the semi-insulating SiC wafer measured using different techniques agree fairly well. As a result, application of removable graphite contacts is proposed for fast and nondestructive resistivity measurement of SiC wafers using the four-point probe method. High-temperature van der Pauw and room-temperature Hall characterization for the tested semi-insulating SiC wafer was also obtained and reported in this work.     

Multipath structure for FSR expansion in waveguide-based optical ring resonator

A multipath structure of a ring resonator is proposed to expand the free spectral range. Simulation work indicates that the multipath ring resonator has 25 GHz-adjacent-channel crosstalk of -41 dB, maximum interchannel crosstalk of -18 dB, and -1 dB bandwidth of 4 GHz for a typical expansion factor of 10. The results show the advantages of characteristics compared with a double-cavity ring resonator and a triple-coupler ring resonator.     

Super-multi-fibre PLC connector utilising angled connection between PLC and tens of fibres

A novel super-multi-fibre planar lightwave circuit (PLC) connector, designed to connect tens of optical fibres and a PLC for super-multichannel PLC-based optical modules with a receptacle interface, is proposed. This connector employs an angled connection instead of a PC connection. A 0.127 mm pitch 32-fibre connector is also demonstrated, which exhibits low connection and high return losses.     

Enhanced Photoelectrochemistry in CdS/Au Nanoparticle Bilayers

Three different configurations of Au‐nanoparticle/CdS‐nanoparticle arrays are organized on Au/quartz electrodes for enhanced photocurrent generation. In one configuration, Au‐nanoparticles are covalently linked to the electrode and the CdS‐nanoparticles are covalently linked to the bare Au‐nanoparticle assembly. The resulting photocurrent, φ = 7.5 %, is ca. 9‐fold higher than the photocurrent originating from a CdS‐nanoparticle layer that lacks the Au‐nanoparticles, φ = 0.8 %. The enhanced photocurrent in the Au/CdS nanoparticle array is attributed to effective charge separation of the electron–hole pair by the injection of conduction‐band electrons from the CdS‐ to the Au‐nanoparticles. Two other configurations involving electrostatically stabilized bipyridinium‐crosslinked Au/CdS or CdS/Au nanoparticle arrays were assembled on the Au/quartz crystal. The photocurrent quantum yields in the two systems are φ = 10 % and φ = 5 %, respectively. The photocurrents in control systems that include electrostatically bridged Au/CdS or CdS/Au nanoparticles by oligocationic units that lack electron‐acceptor units are substantially lower than the values observed in the analogous bipyridinium‐bridged systems. The enhanced photocurrents in the bipyridinium‐crosslinked systems is attributed to the stepwise electron transfer of conduction‐band electrons to the Au‐nanoparticles by the bipyridinium relay bridge, a process that stabilizes the electron–hole pair against recombination and leads to effective charge separation.     

Hf-doped and NH/sub 3/-nitrided high-K gate dielectric thin film with least drain current degradation and flatband voltage shift

A novel technique to form high-K dielectric of HfSiON by doping base oxide with Hf and nitridation with NH/sub 3/, sequentially, is proposed. The HfSiON gate dielectric demonstrates excellent device performances such as only 10% degradation of saturation drain current and almost 45 times of magnitude reduction in gate leakage compared with conventional SiO/sub 2/ gate at the approximately same equivalent oxide thickness. Additionally, negligible flatband voltage shift is achieved with this technique. Time-dependent dielectric breakdown tests indicate that the lifetime of HfSiON is longer than 10 years at V/sub dd/=2 V.