P-N double quantum well resonant interband tunneling diode withpeak-to-valley current ratio of 144 at room temperature

The current-voltage characteristics of the P-N double quantum well resonant interband tunneling (RIT) diodes in InAlAs-InGaAs system have been improved in this letter. The peak-to-valley current ratio (PVCR) is as high as 144 at room temperature. As we know, this is the highest room temperature PVCR ever reported in any tunneling devices. Moreover, the influence of the central barrier thickness varying from 10 Å to 30 Å on the device characteristics is also studied     

Mechanical stress control in a VLSI-fabrication process: a method for obtaining the relation between stress levels and stress-induced failures

An ideal fabrication process is designed to minimize mechanical stress in semiconductor devices and to improve device reliability. Mechanical stress levels were predicted by in-house simulations supported by a thin-film database. These stress levels were correlated with stress-induced defects by TEM analysis supported by fail bit addressing on matured megabit SRAMs. Amorphous-doped silicon film with various annealing temperatures were used for the gate electrode to change the mechanical stress in devices and to get the direct relationship between predicted stress levels and stress related defects. The authors describe brief guidelines for suppressing dislocations in the small geometry shallow-trench isolation process utilizing this system. Polysilicon thickness in the W-polycide gate electrode is designed to minimize mechanical stress in the gate oxide and to suppress the gate oxide failure in probe and class tests. Moreover, critical stress generates dislocations during post source/drain ion implantation anneal obtained by a ball indentation method. This indicated that lower temperature anneal is effective in suppressing the dislocations. A two-step anneal was introduced to suppress dislocations and to enable higher ion activation.     

Low RF noise and power loss for ion-implanted Si having an improved implantation process

Very-low-transmission line noise of <0.25 dB at 18 GHz and low power loss /spl les/0.6 dB at 110 GHz have been measured on transmission lines fabricated on proton-implanted Si. In contrast, a standard Si substrate gave much higher noise of 2.5 dB and worse power loss of 5 dB. The good RF integrity of proton-implanted Si results from the high isolation impedance to ground, as analyzed by an equivalent circuit model. The proton implantation is also done after forming the transmission lines at a reduced implantation energy of /spl sim/4 MeV. This enables easier process integration into current VLSI technology.     

Thermal conductivity of poly(vinyl chloride)/polycaprolactone blends

Thermal diffusivity, heat capacity, and density of polyvinyl chloride/polycaprolactone (PVC/PCL) blends were measured by the laser flash method, DSC, and pycnometry, respectively. The thermal conductivity of the PVC/PCL blends was determined from the results. The miscibility of the blend and crystallinity of PCL were determined by DSC. The effect of blend structure on thermal conductivity is discussed. The phase compositions of the PVC/PCL blends are of three types depending on PCL content: i.e., up to 33%, from 33 to 70%, and above 70% PCL by weight. Thermal conductivity, thermal diffusivity, and heat capacity of the PVC/PCL blends are strongly affected by the phase composition of the blend, which changes in a complicated way with PCL content. © 1994 John Wiley & Sons, Inc.     

Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time /spl Sigma//spl Delta/ ADC

This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-/spl mu/m BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (/spl Sigma//spl Delta/) ADC has 84-dB dynamic range over a total bandwidth of /spl plusmn/135 kHz for an active area of 0.4 mm/sup 2/. Hence, most of the channel filtering is realized in a CMOS IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm/sup 2/.     

Semiconductor optical amplifier for CWDM operating over 1540-1620 nm

A semiconductor optical amplifier was developed for coarse wavelength-division-multiplexing (CWDM) operating over 1540-1620 nm (C-L band). A unique quantum-well structure was designed to meet the requirements for the CWDM operation such as wide bandwidth, low polarization-dependent gain, and high-saturation power at the short wavelength end of the band (1540 nm). Over the band, 24-dB maximum chip gain was obtained with less than 4.3-dB gain flatness and more than 14.6-dBm saturation power.     

ESD phenomena in GMR heads in the manufacturing process of HDD and GMR heads

It is well known that giant magnetoresistive (GMR) heads used for hard disk drives (HDD) are very sensitive to electrostatic discharge (ESD). In this paper, we describe a method of categorizing ESD damage modes from a standpoint of magnetic influences on the heads as observed by quasi-static test (QST) characteristics as well as electromagnetic characteristics like off-track profiles. In addition, we report an example of GMR stack interlayer diffusion which is one type of hard ESD damage. We also present an example of ESD damage that happened in an actual production process and its preventive measures as guidelines.     

Electroluminescence spectroscopy for reliability investigations of 1.55 μm bulk semiconductor optical amplifier

This paper demonstrates the complementary relation between functional parameters and electroluminescence spectroscopy for reliability investigations of 1550 nm Semiconductor Optical Amplifiers of 700 μm length active region. Ageing tests have been set to 270 mA-100 °C-1500 h and realized on two different wafers showing more impact on wafer 1 than on wafer 2. Our investigations are particularly focused on interpretation of electroluminescence spectra, from reference and aged SOAs of wafer 1, leading to an improvement of degradation mechanisms understanding. The shift rate to lower energies of the recombination energy peak at 1550 nm, as reported by electroluminescence spectra between reference and aged SOAs in relation with the decrease of optical power measured at 200 mA for the degraded SOA and completed by I(V) characterizations, suggest occurrence of non radiative deep centers near the buried ridge structure in relation with the cleaning process uniformity of interfaces before epitaxial overgrowth. These defects mainly trap majority injected carriers instead of minority carriers reducing the luminescence in the active zone. By monitoring the most sensitive failure indicator (pseudo-threshold current), lifetime distributions are also calculated to determine failure rate, between 150 and 200 FITs over 15 years for operating conditions (25 °C-200 mA) using experimental degradation laws and statistic computations, demonstrating the overall robustness of this technology.     

Precision winding of fiber optic filament. II. Winding control

For pt.I see ibid., vol.39, no.3, p.258-67 (1992). The winding of fiber optic filament in the hoop, or precision, pattern is considered. Various automatic control options that have been designed and tested are described. The controllers are designed to regulate the fiber lag angle, which is the angle at which the feed filament approaches the take-up spool. Successful, flawless winding is directly related to accurate lag regulation. The contributions are distinguished by the fact that the automatic winding rate is 10 to 30 times greater than that achieved before by operator-assisted winding     

Effects of measurement errors on microwave antenna holography

The effects of measurement errors appearing during the implementation of the microwave holographic technique are investigated in detail, and many representative results are presented based on computer simulations. The numerical results are tailored for cases applicable to the utilization of the holographic technique for the NASA's Deep Space Network antennas, although the methodology of analysis is applicable to any antenna. Many system measurement topics are presented and summarized