Interdiffusion behavior of Hg in HgTe/CdTe superlattices grown on Cd0.96Zn0.04 Te (211)B substrates by molecular beam epitaxy

Double-crystal x-ray rocking curve (DCRC) and secondary-ion mass-spectroscopy (SIMS) measurements have been performed to investigate the effect of rapid thermal annealing on the interdiffusion behavior of Hg in HgTe/CdTe superlattices grown on Cd_0.96Zn_0.04Te (211)B substrates by molecular beam epitaxy. The sharp satellite peaks of the DCRC measurements on a 100-period HgTe/CdTe (100Å/100Å) superlattice show a periodic arrangement of the superlattice with high-quality interfaces. The negative direction of the entropy change obtained from the diffusion coefficients as a function of the reciprocal of the temperature after RTA indicates that the Hg diffusion for the annealed HgTe/CdTe superlattice is caused by an interstitial mechanism. The Cd and the Hg concentration profiles near the annealed HgTe/CdTe superlattice interfaces, as measured by SIMS, show a nonlinear behavior for Hg, originating from the interstitial diffusion mechanism of the Hg composition. These results indicate that a nonlinear interdiffusion behavior is dominant for HgTe/CdTe superlattices annealed at 190°C and that the rectangular shape of HgTe/CdTe superlattices may change to a parabolic shape because of the intermixing of Hg and Cd due to the thermal treatment.     

Novel technique for SiO2 formed by liquid-phasedeposition for low-temperature processed polysilicon TFT

A technique for SiO₂ formation by liquid-phase deposition (LPD) at nearly room temperature for low-temperature processed (LTP) polysilicon thin-film transistor (poly-Si TFT) was developed. LPD SiO₂ film with a lower P-etch rate shows a dense structure. LPD SiO₂ also exhibits good electrical characteristics. LTP poly-Si thin-film transistors (TFTs) with LPD SiO ₂ as the gate insulator have been fabricated and investigated. Their characteristics indicate performance adequate for their use as pixel transistors in liquid crystal displays (LCDs)     

The importance of electrochemistry-related etching in thegate-groove fabrication for InAlAs/InGaAs HFETs

For the first time, the surface metal on nonalloyed ohmic electrodes is found to significantly change the profiles of gate grooves, when resist openings are employed to monitor drain current during wet-chemical gate recess for sub-micron InAlAs/lnGaAs heterojunction field-effect transistors (HFETs). The surface metal of Ni enhances the etching rate in comparison with that in the absence of electrodes by a factor of 4 and 10, laterally and vertically, which is favorable to fabricate deep gate grooves with small side etching. The Pt surface metal, however, leads to preferential etching of InGaAs over InAlAs, which can be useful to realize large side etching. The existence of an electrochemistry-related etching component, which arises when the ohmic electrodes are present during recess etching, is considered to be responsible for these behaviors     

Growth and characterization of hot-wall epitaxial CdTe on (111) HgCdTe and CdZnTe substrates

Thin CdTe films were deposited by hot-wall epitaxy (HWE) on (111) HgCdTe and CdZnTe substrates at temperatures from about 140 to 335°C. X-ray rocking curves were used to show that crystal quality of the CdTe (111)B films improved as substrate temperature increased from 140 to about 250°C. Rocking curve values for full width at half maximum (FWHM) decreased from 2–4 degrees at 140–150°C to less than 100 arc-s at 250°C, and a FWHM of 59 arc-s was the lowest value observed near 250°C. The FWHM of the HWE CdTe was found to be insensitive to growth rate below about 400Å/min, but increased to four degrees at 1250Å/min. X-ray diffraction confirmed that films grown on the B-face at higher temperatures were epitaxial, but contained a significant volume fraction, 35% to 50%, of rotational in-plane twins. Electron microscopy confirmed a coarse twin density, and photoluminescence spectra showed an absence of excitonic emission in the HWE films. Simultaneous growth on two (111) HgCdTe substrates with different surface polarities between 230°C and 335°C showed that deposition rate on the A-face decreased relative to that on the B-face as temperature increased. Films grown on the B-face exhibited better surface morphologies than those grown on the A-face.     

The epitaxial growth of gaas using alkylarsine: Part 2. molecular orbital calculation

Semi-empirical molecular orbital calculations were carried out for the compounds (C₂H₅)₃As, (C₂H₅)₃Ga and RAsH₂ (R = C₂H₅, i-C₃H₇, i-C₄H₉, and t-C₄H₉) by using the CNDO/2-U program, and their capability of β-elimination reaction is compared on the basis of the torsion energy to the transition state, electrostatic interactions and orbital overlapping between the central atom and the β-hydrogen, and bond order of the metal-carbon, and carbon-hydrogen bond. In the comparison of (C₂H₅)₃As with (C₂H₅)₃Ga, we found that the β-elimination of (C₂H₅)₃As could hardly be expected to take place in the thermal decomposition. The capability of β-elimination would be smaller in C₂H₅AsH₂ than that in (C₂H₅)₃As. Moreover when the ethyl group is replaced by a t-butyl group in RAsH₂, the β-elimination reaction appears to become more difficult and a large possibility for a radical process is suggested.     

Resolvability theory for the multiple-access channel

We study the randomness needed for approximating the output distribution of a multiple-access channel, where the original input processes are independent of each other. The approximation is achieved by simulating (possibly alternative) input processes at each of the entries, where the sources of randomness available for the simulators are independent of each other, and the simulators do not cooperate. The resolvability region of a multiple-access channel is defined as the set of all random-bit rate pairs at which accurate output approximation is possible, where the simulation accuracy is measured by the variational distance between finite-dimensional output distributions. Inner and outer bounds on the resolvability region are derived, and close relations between the concepts of resolvability region and capacity region are demonstrated     

The relation between luminous properties and oxygen content inZnS:TbOF thin-film electroluminescent devices fabricated byradio-frequency magnetron sputtering method

The purpose of this paper is to study the relationship between the oxygen concentration and brightness degradation in ZnS:TbOF green thin-film electroluminescent (EL) devices. The characteristics including crystallinity, optical, and electrical properties were discussed. The brightness-voltage (B-V) measurement results shelved that with higher oxygen-content in ZnS:TbOF phosphor layer, lower brightness was measured. It was consistent with the poor crystallinity, worse photoluminescent intensity, and easier to get moisture in the oxygen-rich (O/Tb>1) phosphor film. Furthermore, deep level transient spectroscopy (DLTS) measurements identified that when the O/Tb ratio was greater than 1, the oxygen-related deep hole traps E_H1 and/or E_H2 could be detected in the ZnS:TbOF phosphor layer. These E _H1 and/or E_H2 traps were believed to be the main killers for the brightness of the device since they capture most of the holes from the generated electron-hole pairs. This evidence strongly supports that the modified energy transfer model is more dominant than direct impact excitation during the luminescent process     

A floating-gate analog memory device for neural networks

A floating-gate MOSFET device that can be used as a precision analog memory for neural network LSIs is described. This device has two floating gates. One is a charge-injection gate with a Fowler-Nordheim tunnel junction, and the other is a charge-storage gate that operates as a MOSFET floating gate. The gates are connected by high resistance, and the charge-injection gate is small so that its capacitance is much less than that of the charge-storage gate. By applying control pulses to the charge-injection gate, it is possible to charge and discharge the MOSFET floating gate in order to modify the MOSFET current with high resolution over 10 b. The charge injection can be carried out without disturbing the MOSFET output current with high voltage control pulses. This device is useful for on-chip learning in analog neural network LSIs     

P-MOSFET's with ultra-shallow solid-phase-diffused drain structureproduced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1-μm and sub-0.1-μm devices. Highly doped ultrashallow p⁺ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p⁺-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved     

Dynamic programming implementation on array processor architectures

Dynamic Programming (DP) applies to many signal and image processing applications including boundary following, the Viterbi algorithm, dynamic time warping, etc. This paper presents an array processor implementation of generic dynamic programming. Our architecture is a SIMD array attached to a host computer. The processing element of the architecture is based on an ASIC design opting for maximum speed-up. By adopting a torus interconnection network, a dual buffer structure, and a multilevel pipeline, the performance of the DP chip is expected to reach the order of several GOPS. The paper discusses both the dedicated hardware design and the data flow control of the DP chip and the total array.This work was supported in part by the NATO, Scientific and Environmental Affairs Division, Collaborative Research Grant SA.5-2-05(CRG.960201)424/96/JARC-501.