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111.
Jin Xie Yun-Wei Song Dr. Bo-Quan Li Dr. Hong-Jie Peng Prof. Jia-Qi Huang Prof. Qiang Zhang 《Angewandte Chemie (Weinheim an der Bergstrasse, Germany)》2020,132(49):22334-22339
Polysulfide intermediates (PSs), the liquid-phase species of active materials in lithium–sulfur (Li-S) batteries, connect the electrochemical reactions between insulative solid sulfur and lithium sulfide and are key to full exertion of the high-energy-density Li-S system. Herein, the concept of sulfur container additives is proposed for the direct modification on the PSs species. By reversible storage and release of the sulfur species, the container molecule converts small PSs into large organosulfur species. The prototype di(tri)sulfide-polyethylene glycol sulfur container is highly efficient in the reversible PS transformation to multiply affect electrochemical behaviors of sulfur cathodes in terms of liquid-species clustering, reaction kinetics, and solid deposition. The stability and capacity of Li-S cells was thereby enhanced. The sulfur container is a strategy to directly modify PSs, enlightening the precise regulation on Li-S batteries and multi-phase electrochemical systems. 相似文献
112.
Dong‐Wook Kim 《ETRI Journal》2006,28(1):84-86
This letter presents a small‐sized, high‐power single‐pole double‐throw (SPDT) switch with defected ground structure (DGS) for wireless broadband Internet application. To reduce the circuit size by using a slow‐wave characteristic, the DGS is used for the quarter‐wave (°/4) transmission line of the switch. To secure a high degree of isolation, the switch with DGS is composed of shunt‐connected PIN diodes. It shows an insertion loss of 0.8 dB, an isolation of 50 dB or more, and power capability of at least 50 W at 2.3 GHz. The switch shows very similar performance to the conventional shunt‐type switch, but the circuit size is reduced by about 50% simply with the use of DGS patterns. 相似文献
113.
High-performance and power-efficient CMOS comparators 总被引:1,自引:0,他引:1
Chung-Hsun Huang Jinn-Shyan Wang 《Solid-State Circuits, IEEE Journal of》2003,38(2):254-262
Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques. 相似文献
114.
115.
Rogin J. Kouchev I. Brenna G. Tschopp D. Qiuting Huang 《Solid-State Circuits, IEEE Journal of》2003,38(12):2239-2248
A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW. 相似文献
116.
W. Shieh R. Hui X. Yi 《Photonics Technology Letters, IEEE》2006,18(10):1122-1124
We perform a systematic measurement of the degree-of-polarization (DOP) and eye-closure penalty for optical signals with orthogonal polarizations. We find that the symmetry of DOP is maintained for the orthogonal polarizations under both first and higher order polarization-mode dispersion (PMD), whereas the symmetry of eye-closure penalty is broken under second-order PMD. An orthogonal polarization pair can have large disparity of eye-closure penalty despite an identical DOP. We also demonstrate a novel approach to estimate the maximum eye-closure penalty asymmetry with three orthogonal polarizations on the Poincare/spl acute/ sphere. 相似文献
117.
Analysis and architecture design of variable block-size motion estimation for H.264/AVC 总被引:1,自引:0,他引:1
Ching-Yeh Chen Shao-Yi Chien Yu-Wen Huang Tung-Chien Chen Tu-Chih Wang Liang-Gee Chen 《IEEE transactions on circuits and systems. I, Regular papers》2006,53(3):578-593
Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory. 相似文献
118.
Hyun‐Cheol Kim Charalampos Z. Patrikakis Nikos Minogiannis Pantelis N. Karamolegkos Alex Lambiris Kyuheon Kim 《ETRI Journal》2006,28(4):411-424
This paper presents a multimedia streaming platform for efficiently transmitting MPEG‐4 content over IP networks. The platform includes an MPEG‐4 compliant streaming server and client, supporting object‐based representation of multimedia scenes, interactivity, and advanced encoding profiles defined by the ISO standard. For scalability purposes, we employ an application‐layer multicast scheme for media transmission using overlay networks. The overlay network, governed by the central entity of the network distribution manager, is dynamically deployed according to a set of pre‐defined criteria. The overlay network supports both broadcast delivery and video‐on‐demand content. The multimedia streaming platform is standards‐compliant and utilizes widespread multimedia protocols such as MPEG‐4, real‐time transport protocol, real‐time transport control protocol, and real‐time streaming protocol. The design of the overlay network was architected with the goal of transparency to both the streaming server and the client. As a result, many commercial implementations that use industry‐standard protocols can be plugged into the architecture relatively painlessly and can enjoy the benefits of the platform. 相似文献
119.
实验室的质量监督(上) 总被引:4,自引:0,他引:4
质量监督是实验室保持人员能力,进行自我完善,日常渐进的重要手段,是持续改进的重要组成部分,也是实验室管理工作的难点,本文给出质量监督的目的、对象、方法、记录等. 相似文献
120.