GaAs亚微米自对准工艺技术研究

总结了在５０ｍｍＧａＡｓ圆片上实现自对准介质膜隔离等平面工艺技术的研究，着重描述了离子注入、自对准亚微米难熔栅制备、钝化介质膜生长、干法刻蚀、电阻和电容制备等关键工艺的研究结果。这套工艺的均匀性、重复性好，在５０ｍｍＧａＡｓ圆片上获得了满意的成品率。采用这套工艺已成功地研制出多种性能良好的ＧａＡｓＩＣ和ＧａＡｓ功率ＭＥＳＦＥＴ，证明国家自然科学基金委员会这一重大课题的选择对发展我国ＧａＡｓＩＣ确实具有重大意义。     

2～12GHz GaAs单片行波放大器

报道了一个全平面超宽带ＧａＡｓ单片行波放大器的研究结果。该单片电路的核心部件是四个３００μｍ栅宽的ＭＥＳＦＥＴ，整个电路拓扑结构简单，芯片面积为３．０ｍｍ×１．８ｍｍ。电路经优化设计后在２～１２ＧＨｚ范围内，小信号增益为５±１ｄＢ，输入输出电压驻波比≤１．７５。上述频率范围内输出功率≥１６ｄＢｍ，噪声系数≤８ｄＢ。采用全离子注入、全平面工艺，均匀性、一致性良好。实验结果与设计预计值十分一致。     

温度调谐LBO晶体光参量振荡器

本文详细研究０．５３２μｍ激光泵浦、温度调谐Ⅱ型非临界相位匹配ＬＢＯ光参量振荡器。当温度从２０℃升高到２００℃时，其信号波和闲置波的调谐范围分别为１．００２～０．８９８μｍ和１．１３４～１．３０６μｍ。本装置最吸引人之处是本征输出线宽比Ⅰ型情形小一个量级。     

双波长Nd：YAG脉冲激光器的实验研究

根据多波长同时振荡条件，我们建立了大能量１０６４ｎｍ和１３１８ｎｍ同时运转的双波长脉冲Ｎｄ：ＹＡＧ激光器。得到了１０６４ｎｍ和１３１８ｎｍ的激光输出能量分别为０．５９４Ｊ和０．８６１Ｊ，效率分别为０．３１％和０．４５％。实验结果说明了该双波长激光器有较好的时间和空间重选性。     

A simple method for extracting average doping concentration in thepolysilicon and silicon surface layer near the oxide in polysilicon-gateMOS structures

The author demonstrates a simple technique that extracts average doping concentration in the polysilicon and silicon near the oxide in a metal/polysilicon/oxide/silicon system. The technique is based on the maximum-minimum capacitance method on two large area structures-one MOSFET and one MOSC (MOS capacitor). The technique is simple and reliable since only three data points in the C-V data are required-two points in MOSC C-V and one point in MOSFET C-V. The technique avoids inaccuracy caused by interface traps at the polysilicon/oxide and the oxide/silicon interface. The technique can be implemented into fab routine electric-test procedures for simultaneously monitoring change of doping concentration in polysilicon and silicon during process development     

Enhancement of oxide break-up by implantation of fluorine inpoly-Si emitter contacted p+-n shallow junctionformation

In this study, it is demonstrated that the incorporation of fluorine can enhance poly-Si/Si interfacial oxide break-up in the poly-Si emitter contacted p⁺-n shallow junction formation. The annealing temperature for breaking up the poly-Si/Si interfacial oxide has been found to be as low as 900°C. As a result, the junction depth of the BF₂-implanted device is much larger than that of the boron-implanted device     

InGaN/GaN MQW p–n junction photodetectors

InGaN/GaN multiquantum well (MQW) p–n junction photodetectors with semi-transparent Ni/Au electrodes were fabricated and characterized. It was found that the fabricated InGaN/GaN MQW p–n junction photodetectors exhibit a 20 V breakdown voltage and a 3.5 V forward 20 mA turn on voltage. It was also found that the photocurrent to dark current contrast ratio is higher than 10⁵ when a 0.4 V reverse bias was applied to the InGaN/GaN MQW p–n junction photodetectors. Furthermore, it was found that the maximum responsivity was 1.28 and 1.76 A/W with a 0.1 and 3 V applied reverse bias, respectively.     

High temperature superconducting thin films for microwave filters

YBa₂Cu₃O_7-δ and Tl₂Ba₂CaCu₂O₈ thin films for microwave filters were synthesized by pulsed laser deposition and the two-step thalliation process. Substrate quality requirements and the relation of thin film morphology, microstructure with microwave surface resistance were discussed.     

Design of a 3780-point IFFT processor for TDS-OFDM

This correspondence presents a design of 3780-point IFFT processor for TDS-OFDM terrestrial DTV transmitter using FPGA. It demonstrates the algorithm design and error analysis of the processor, which can achieve a throughput of 7.56M complex IFFT operations per second. This design meets the signal-to-quantization noise ratio requirement of the TDS-OFDM system. It consists of two FPGA and one dual-port RAM. The data stream pipeline algorithm is implemented     

A quadruple well, quadruple polysilicon BiCMOS process for fast 16Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 μm² with conventional I-line lithography and 7.32 μm² with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 μm active pitch, MOSFET transistors designed for a 0.80 μm gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance