薄膜干涉型光学全通滤波器的设计与分析

设计并分析了用于多信道色谱补偿的薄膜Gires-Tournois干涉仪（GTI）型光学全通滤波（OAPF），讨论了反射镜的膜层结构对器件 的群延迟谱和反射谱的影响，。以及大角度入射引起的偏分离现象和幅度畸变现象，给出了单级和多级串拉OAPF的初步设计结果。     

Solaris2.X操作系统上NFS的环境配置

本文描述了Ｓｏｌａｒｉｓ２．Ｘ操作系统上网络文件系统ＮＦＳ的特性及其环境配置，介绍了如何建立了ＮＦＳ服务器和ＮＦＳ客户机，从而实现了远程文件系统资源共享。     

小型RFCO2激光器的电路保护

本文详细分析研究了小型射频CO2激光器经常出现的故障现象(过压、负载短路故障),并介绍了相应的保护措施,对实际工作有显着指导意义。     

An assessment of potential nonlinear circuit models for thecharacterization of resonant tunneling diodes

The intrinsically fast process of resonant tunneling through double barrier heterostructures along with the existence of negative differential resistance in the current-voltage characteristic of these structures has led to their implementation as sources for high frequency electromagnetic energy. While sources based upon resonant tunneling diodes (RTDs) have produced frequency of oscillations up to 712 GHz, only microwatt levels of performance has been achieved above 100 GHz. Since stability criteria plays critical role in determining the deliverable power of any oscillator, a physically accurate equivalent-circuit model for the RTD is extremely important for optimizing the dynamics of the device-cavity package. This study identifies a distinctly new equivalent circuit model for characterizing the modes of oscillation in RTD-based sources. Specifically, in order to exhibit the fundamental self-oscillations and the overall I-V characteristics (plateau structure and hysteresis) observed experimentally, an accurate circuit model of the RTD must incorporate: (i) a quantum-well inductance which directly chokes the nonlinear conductance and, (ii) a nonlinear access resistance, associated with the accumulation of charge in the injection region of the double barriers, with a nonlocal dependence on the bias across the double barrier structure     

Analysis of thermal instability in multi-finger power AlGaAs/GaAsHBT's

A new theory is developed in this paper to explain the collapse of current gain in multi-finger power AlGaAs/GaAs Heterojunction Bipolar Transistors (HBT's). The reasons behind this unwanted phenomenon are fully clarified using a simple model to investigate the thermo-electrical interaction between the fingers. The existence of multi-value equilibrium points in model's constitutive equations is shown to be the necessary condition for the collapse of current gain to appear. For a N-finger device, N different patterns of collapse exist. The criterion to select the global stable pattern is given. The method has been used to predict the collapse in AlGaAs/GaAs HBT's and the agreement is excellent. The method also predicts that the collapse can happen far earlier than is normally expected in multi-finger high-power devices. The influence of ballasting resistance and thermal resistance is also investigated     

钢管内径光电检测装置

介绍了一种检测细长钢管内径的光电检测装置。该装置利用线阵ＣＣＤ作传感器，采用８０３１单片机作为主控制。     

Measurement and modeling of the sidewall threshold voltage ofmesa-isolated SOI MOSFETs

Five-terminal silicon-on-insulator (SOI) MOSFETs have been characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with the body bias at the front and back interfaces can be explained by the standard bulk body effect equation. However, the threshold voltage shift at the sidewall is smaller than predicted by this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model that accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation is discussed. The model makes it possible to measure the sidewall threshold even when it is larger than the front threshold voltage     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.